[Intel-gfx] [PATCH 6/6] drm/i915: Implement PSR2 selective fetch WAs

[José Roberto de Souza]

This feature have 3 WAs and as commented WA 14010103792 and
WA 14010254185 conflicts, so leaving the feature disabled in the
affected steppings.

Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h          |  1 +
 2 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index bc2a2e64fe2a..c138ab69fa93 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -518,13 +518,21 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
        else
                val |= EDP_PSR2_TP2_TIME_2500us;
 
-       if (dev_priv->psr.psr2_sel_fetch_enabled)
+       if (dev_priv->psr.psr2_sel_fetch_enabled) {
+               /* WA 1408330847 */
+               if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+                   IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
+                       intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
+                                    DIS_RAM_BYPASS_PSR2_MAN_TRACK,
+                                    DIS_RAM_BYPASS_PSR2_MAN_TRACK);
+
                intel_de_write(dev_priv,
                               PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder),
                               PSR2_MAN_TRK_CTL_ENABLE);
-       else if (HAS_PSR2_SEL_FETCH(dev_priv))
+       } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
                intel_de_write(dev_priv,
                               PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0);
+       }
 
        /*
         * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
@@ -651,6 +659,17 @@ static bool intel_psr2_sel_fetch_config_valid(struct 
intel_dp *intel_dp,
                return false;
        }
 
+       /*
+        * As WA 14010103792 conflicts with WA 14010254185 so disabling PSR2 SW
+        * tracking in TGL and RKL A0
+        */
+       if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+           IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)) {
+               drm_dbg_kms(&dev_priv->drm,
+                           "PSR2 sel fetch not enabled, feature not working in 
current stepping\n");
+               return false;
+       }
+
        if (crtc_state->uapi.async_flip) {
                drm_dbg_kms(&dev_priv->drm,
                            "PSR2 sel fetch not enabled, async flip enabled\n");
@@ -1063,6 +1082,13 @@ static void intel_psr_disable_locked(struct intel_dp 
*intel_dp)
                                    psr_status_mask, 2000))
                drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
 
+       /* WA 1408330847 */
+       if (dev_priv->psr.psr2_sel_fetch_enabled &&
+           (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+            IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
+               intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
+                            DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
+
        /* Disable PSR on Sink */
        drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6f547e459d30..2e374e166b2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7833,6 +7833,7 @@ enum {
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE                (1 << 2)
 
 #define CHICKEN_PAR1_1                 _MMIO(0x42080)
+#define  DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16)
 #define  SKL_DE_COMPRESSED_HASH_MODE   (1 << 15)
 #define  DPA_MASK_VBLANK_SRD           (1 << 15)
 #define  FORCE_ARB_IDLE_PLANES         (1 << 14)
-- 
2.26.2

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