On Thu, 2025-03-20 at 00:45 +0530, Animesh Manna wrote: > For every commit the dependent condition for LOBF is checked > and accordingly update has_lobf flag which will be used > to update the ALPM_CTL register during commit. > > v1: Initial version. > v2: Avoid reading h/w register without has_lobf check. [Jani] > v3: Update LOBF in post plane update instead of separate function. > [Jouni] > > Signed-off-by: Animesh Manna <animesh.ma...@intel.com> > --- > drivers/gpu/drm/i915/display/intel_alpm.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c > b/drivers/gpu/drm/i915/display/intel_alpm.c > index c2862888466f..5df1253a6b6c 100644 > --- a/drivers/gpu/drm/i915/display/intel_alpm.c > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c > @@ -378,9 +378,12 @@ void intel_alpm_post_plane_update(struct > intel_atomic_state *state, > struct intel_display *display = to_intel_display(state); > const struct intel_crtc_state *crtc_state = > intel_atomic_get_new_crtc_state(state, crtc); > + const struct intel_crtc_state *old_crtc_state = > + intel_atomic_get_old_crtc_state(state, crtc); > struct intel_encoder *encoder; > > - if (!crtc_state->has_lobf && !crtc_state->has_psr) > + if (!crtc_state->has_lobf && !crtc_state->has_psr && > + !old_crtc_state->has_lobf)
I don't really understand this change? Where lobf is disabled when has_lobf is false? BR, Jouni Högander > return; > > for_each_intel_encoder_mask(display->drm, encoder,
