Now that DG2 has a DPLL manager and its users are prepared to obtain clock state through the framework, switch the platform over to use the shared DPLL manager.
Remove specific MPLLB state verification and use .compare_hw function hook to compare HW and SW PLL states. Assisted-by: Copilot:claude-sonnet-4-6 Signed-off-by: Mika Kahola <[email protected]> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 - drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++-- .../drm/i915/display/intel_modeset_verify.c | 1 - drivers/gpu/drm/i915/display/intel_snps_phy.c | 49 ------------------- 4 files changed, 8 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index b6799ed24de4..1c4820430b68 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -5330,8 +5330,6 @@ void intel_ddi_init(struct intel_display *display, else encoder->get_config = mtl_ddi_non_tc_phy_get_config; } else if (display->platform.dg2) { - encoder->enable_clock = intel_mpllb_enable; - encoder->disable_clock = intel_mpllb_disable; encoder->get_config = dg2_ddi_get_config; } else if (display->platform.alderlake_s) { encoder->enable_clock = adls_ddi_enable_clock; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index c03560532d94..6678188e3563 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -4950,7 +4950,6 @@ static bool dg2_compare_hw_state(const struct intel_dpll_hw_state *_a, a->mpllb_sscstep == b->mpllb_sscstep; } -__maybe_unused static const struct intel_dpll_mgr dg2_pll_mgr = { .dpll_info = dg2_plls, .compute_dplls = dg2_compute_dplls, @@ -4977,8 +4976,7 @@ void intel_dpll_init(struct intel_display *display) mutex_init(&display->dpll.lock); if (display->platform.dg2) - /* No shared DPLLs on DG2; port PLLs are part of the PHY */ - dpll_mgr = NULL; + dpll_mgr = &dg2_pll_mgr; else if (DISPLAY_VER(display) >= 35) dpll_mgr = &xe3plpd_pll_mgr; else if (DISPLAY_VER(display) >= 14) @@ -5347,8 +5345,13 @@ verify_single_dpll_state(struct intel_display *display, if (pll->on) { const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; - - if (HAS_LT_PHY(display)) + /* + * Avoid direct struct comparison here. Some hw state fields, such + * as DG2 MPLLB ref_control or LT PHY config[1], are written by + * firmware and may differ from the software state without indicating + * a real mismatch. + */ + if (HAS_LT_PHY(display) || display->platform.dg2) pll_mismatch = !dpll_mgr->compare_hw_state(&pll->state.hw_state, &dpll_hw_state); else diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index 2ec17c2bfe0f..f0761d8a7437 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -245,7 +245,6 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state, verify_connector_state(state, crtc); verify_crtc_state(state, crtc); intel_dpll_state_verify(state, crtc); - intel_mpllb_state_verify(state, crtc); } void intel_modeset_verify_disabled(struct intel_atomic_state *state) diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index dfb3a5c35c85..ce94ac689064 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -1982,52 +1982,3 @@ void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, */ pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN; } - -void intel_mpllb_state_verify(struct intel_atomic_state *state, - struct intel_crtc *crtc) -{ - struct intel_display *display = to_intel_display(state); - const struct intel_crtc_state *new_crtc_state = - intel_atomic_get_new_crtc_state(state, crtc); - struct intel_mpllb_state mpllb_hw_state = {}; - const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb; - struct intel_encoder *encoder; - - if (!display->platform.dg2) - return; - - if (!new_crtc_state->hw.active) - return; - - /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */ - if (!intel_crtc_needs_modeset(new_crtc_state) && - !intel_crtc_needs_fastset(new_crtc_state)) - return; - - encoder = intel_get_crtc_new_encoder(state, new_crtc_state); - intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); - -#define MPLLB_CHECK(__name) \ - INTEL_DISPLAY_STATE_WARN(display, mpllb_sw_state->__name != mpllb_hw_state.__name, \ - "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \ - crtc->base.base.id, crtc->base.name, \ - __stringify(__name), \ - mpllb_sw_state->__name, mpllb_hw_state.__name) - - MPLLB_CHECK(mpllb_cp); - MPLLB_CHECK(mpllb_div); - MPLLB_CHECK(mpllb_div2); - MPLLB_CHECK(mpllb_fracn1); - MPLLB_CHECK(mpllb_fracn2); - MPLLB_CHECK(mpllb_sscen); - MPLLB_CHECK(mpllb_sscstep); - - /* - * ref_control is handled by the hardware/firemware and never - * programmed by the software, but the proper values are supplied - * in the bspec for verification purposes. - */ - MPLLB_CHECK(ref_control); - -#undef MPLLB_CHECK -} -- 2.43.0
