> -----Original Message----- > From: Intel-wired-lan <[email protected]> On Behalf Of > Arkadiusz Kubalewski > Sent: Monday, December 18, 2023 8:29 PM > To: [email protected] > Cc: Loktionov, Aleksandr <[email protected]>; Kitszel, Przemyslaw > <[email protected]>; Kubalewski, Arkadiusz > <[email protected]> > Subject: [Intel-wired-lan] [PATCH iwl-net v2] ice: dpll: fix phase offset > value > > Stop dividing the phase_offset value received from firmware. This fault > is present since the initial implementation. > The phase_offset value received from firmware is in 0.01ps resolution. > Dpll subsystem is using the value in 0.001ps, raw value is adjusted > before providing it to the user. > > The user can observe the value of phase offset with response to > `pin-get` netlink message of dpll subsystem for an active pin: > $ ./tools/net/ynl/cli.py --spec Documentation/netlink/specs/dpll.yaml \ > --do pin-get --json '{"id":2}' > > Where example of correct response would be: > {'board-label': 'C827_0-RCLKA', > 'capabilities': 6, > 'clock-id': 4658613174691613800, > 'frequency': 1953125, > 'id': 2, > 'module-name': 'ice', > 'parent-device': [{'direction': 'input', > 'parent-id': 6, > 'phase-offset': -216839550, > 'prio': 9, > 'state': 'connected'}, > {'direction': 'input', > 'parent-id': 7, > 'phase-offset': -42930, > 'prio': 8, > 'state': 'connected'}], > 'phase-adjust': 0, > 'phase-adjust-max': 16723, > 'phase-adjust-min': -16723, > 'type': 'mux'} > > Provided phase-offset value (-42930) shall be divided by the user with > DPLL_PHASE_OFFSET_DIVIDER to get actual value of -42.930 ps. > > Before the fix, the response was not correct: > {'board-label': 'C827_0-RCLKA', > 'capabilities': 6, > 'clock-id': 4658613174691613800, > 'frequency': 1953125, > 'id': 2, > 'module-name': 'ice', > 'parent-device': [{'direction': 'input', > 'parent-id': 6, > 'phase-offset': -216839, > 'prio': 9, > 'state': 'connected'}, > {'direction': 'input', > 'parent-id': 7, > 'phase-offset': -42, > 'prio': 8, > 'state': 'connected'}], > 'phase-adjust': 0, > 'phase-adjust-max': 16723, > 'phase-adjust-min': -16723, > 'type': 'mux'} > > Where phase-offset value (-42), after division > (DPLL_PHASE_OFFSET_DIVIDER) would be: -0.042 ps. > > Fixes: 8a3a565ff210 ("ice: add admin commands to access cgu configuration") > Fixes: 90e1c90750d7 ("ice: dpll: implement phase related callbacks") > Reviewed-by: Aleksandr Loktionov <[email protected]> > Reviewed-by: Przemek Kitszel <[email protected]> > Signed-off-by: Arkadiusz Kubalewski <[email protected]> > --- > drivers/net/ethernet/intel/ice/ice_common.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) >
Tested-by: Pucha Himasekhar Reddy <[email protected]> (A Contingent worker at Intel) _______________________________________________ Intel-wired-lan mailing list [email protected] https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
