> -----Original Message----- > From: Intel-wired-lan <[email protected]> On Behalf Of > Grzegorz Nitka > Sent: 05 November 2024 17:59 > To: [email protected] > Cc: [email protected]; Kubalewski, Arkadiusz > <[email protected]>; Kolacinski, Karol > <[email protected]>; Nguyen, Anthony L <[email protected]>; > Kitszel, Przemyslaw <[email protected]> > Subject: [Intel-wired-lan] [PATCH v4 iwl-net 4/4] ice: Add correct PHY lane > assignment > > From: Karol Kolacinski <[email protected]> > > Driver always naively assumes, that for PTP purposes, PHY lane to configure > is corresponding to PF ID. > > This is not true for some port configurations, e.g.: > - 2x50G per quad, where lanes used are 0 and 2 on each quad, but PF IDs > are 0 and 1 > - 100G per quad on 2 quads, where lanes used are 0 and 4, but PF IDs are > 0 and 1 > > Use correct PHY lane assignment by getting and parsing port options. > This is read from the NVM by the FW and provided to the driver with the > indication of active port split. > > Remove ice_is_muxed_topo(), which is no longer needed. > > Fixes: 4409ea1726cb ("ice: Adjust PTP init for 2x50G E825C devices") > Reviewed-by: Przemek Kitszel <[email protected]> > Reviewed-by: Arkadiusz Kubalewski <[email protected]> > Signed-off-by: Karol Kolacinski <[email protected]> > Signed-off-by: Grzegorz Nitka <[email protected]> > --- > V1 -> V3: Added checker for speed value in returned AQ Get Options > > .../net/ethernet/intel/ice/ice_adminq_cmd.h | 1 + > drivers/net/ethernet/intel/ice/ice_common.c | 45 +++++++++++++++++++ > drivers/net/ethernet/intel/ice/ice_common.h | 1 + > drivers/net/ethernet/intel/ice/ice_main.c | 6 +-- > drivers/net/ethernet/intel/ice/ice_ptp.c | 23 ++++------ > drivers/net/ethernet/intel/ice/ice_ptp.h | 4 +- > drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 26 +---------- > drivers/net/ethernet/intel/ice/ice_type.h | 1 - > 8 files changed, 62 insertions(+), 45 deletions(-) >
Tested-by: Pucha Himasekhar Reddy <[email protected]> (A Contingent worker at Intel)
