> -----Original Message-----
> From: Intel-wired-lan <[email protected]> On Behalf Of Simon
> Horman
> Sent: Friday, December 6, 2024 5:17 AM
> To: Kolacinski, Karol <[email protected]>
> Cc: [email protected]; [email protected]; Nguyen, Anthony
> L <[email protected]>; Kitszel, Przemyslaw
> <[email protected]>
> Subject: Re: [Intel-wired-lan] [PATCH v3 iwl-next] ice: Add in/out PTP pin
> delays
>
> On Wed, Dec 04, 2024 at 10:46:11AM +0100, Karol Kolacinski wrote:
>> HW can have different input/output delays for each of the pins.
>>
>> Currently, only E82X adapters have delay compensation based on TSPLL
>> config and E810 adapters have constant 1 ms compensation, both cases
>> only for output delays and the same one for all pins.
>>
>> E825 adapters have different delays for SDP and other pins. Those
>> delays are also based on direction and input delays are different than
>> output ones. This is the main reason for moving delays to pin
>> description structure.
>>
>> Add a field in ice_ptp_pin_desc structure to reflect that. Delay values
>> are based on approximate calculations of HW delays based on HW spec.
>>
>> Implement external timestamp (input) delay compensation.
>>
>> Remove existing definitions and wrappers for periodic output propagation
>> delays.
>>
>> Reviewed-by: Przemek Kitszel <[email protected]>
>> Signed-off-by: Karol Kolacinski <[email protected]>
>> ---
>> V2 -> V3: rebased, renamed prop_delay to prop_delay_ns, reworded commit
>> message to be more descriptive
>> V1 -> V2: removed duplicate gpio_pin variable and restored missing
>> ICE_E810_E830_SYNC_DELAY
>
> Reviewed-by: Simon Horman <[email protected]>
>
Tested-by: Sunitha Mekala <[email protected]> (A Contingent worker at
Intel)
