> -----Original Message----- > From: Intel-wired-lan <[email protected]> On Behalf Of > Grzegorz Nitka > Sent: 20 March 2025 18:46 > To: [email protected] > Cc: [email protected]; Kolacinski, Karol <[email protected]>; > [email protected]; Kitszel, Przemyslaw <[email protected]> > Subject: [Intel-wired-lan] [PATCH iwl-next v3 3/3] ice: enable timesync > operation on 2xNAC E825 devices > > From: Karol Kolacinski <[email protected]> > > According to the E825C specification, SBQ address for ports on a single > complex is device 2 for PHY 0 and device 13 for PHY1. > For accessing ports on a dual complex E825C (so called 2xNAC mode), the > driver should use destination device 2 (referred as phy_0) for the current > complex PHY and device 13 (referred as phy_0_peer) for peer complex PHY. > > Differentiate SBQ destination device by checking if current PF port number is > on the same PHY as target port number. > > Adjust 'ice_get_lane_number' function to provide unique port number for ports > from PHY1 in 'dual' mode config (by adding fixed offset for PHY1 ports). > Cache this value in ice_hw struct. > > Introduce ice_get_primary_hw wrapper to get access to timesync register not > available from second NAC. > > Reviewed-by: Simon Horman <[email protected]> > Reviewed-by: Przemek Kitszel <[email protected]> > Signed-off-by: Karol Kolacinski <[email protected]> > Co-developed-by: Grzegorz Nitka <[email protected]> > Signed-off-by: Grzegorz Nitka <[email protected]> > --- > drivers/net/ethernet/intel/ice/ice.h | 60 ++++++++++++++++++++- > drivers/net/ethernet/intel/ice/ice_common.c | 6 ++- > drivers/net/ethernet/intel/ice/ice_ptp.c | 49 ++++++++++++----- > drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 39 +++++++++++--- > drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 5 -- > drivers/net/ethernet/intel/ice/ice_type.h | 1 + > 6 files changed, 134 insertions(+), 26 deletions(-) >
Tested-by: Rinitha S <[email protected]> (A Contingent worker at Intel)
