On Tue, 10 Jun 2025 06:04:34 +0200 Arkadiusz Kubalewski wrote:
> +The device may support the Reference SYNC feature, which allows the
> combination
> +of two inputs into a input pair. In this configuration, clock signals
> +from both inputs are used to synchronize the dpll device. The higher
> frequency
^^^^
DPLL ?
> +signal is utilized for the loop bandwidth of the DPLL, while the lower
> frequency
> +signal is used to syntonize the output signal of the DPLL device. This
> feature
> +enables the provision of a high-quality loop bandwidth signal from an
> external
> +source.
Looks like there is a conflict between this series and patches sent
by Tony the day before. You'll have to rebase.
--
pw-bot: cr
