> -----Original Message-----
> From: Intel-wired-lan <[email protected]> On Behalf
> Of Ivan Vecera
> Sent: Thursday, January 8, 2026 7:23 PM
> To: [email protected]
> Cc: Eric Dumazet <[email protected]>; Nguyen, Anthony L
> <[email protected]>; Rob Herring <[email protected]>; Leon
> Romanovsky <[email protected]>; Andrew Lunn <[email protected]>;
> [email protected]; Kitszel, Przemyslaw
> <[email protected]>; Kubalewski, Arkadiusz
> <[email protected]>; [email protected];
> Jakub Kicinski <[email protected]>; Paolo Abeni <[email protected]>;
> [email protected]; Conor Dooley <[email protected]>; Jiri
> Pirko <[email protected]>; Richard Cochran <[email protected]>;
> Prathosh Satish <[email protected]>; Vadim Fedorenko
> <[email protected]>; Mark Bloch <[email protected]>; linux-
> [email protected]; Tariq Toukan <[email protected]>; Lobakin,
> Aleksander <[email protected]>; Jonathan Lemon
> <[email protected]>; Krzysztof Kozlowski <[email protected]>;
> Saeed Mahameed <[email protected]>; David S. Miller
> <[email protected]>
> Subject: [Intel-wired-lan] [PATCH net-next 12/12] ice: dpll: Support
> E825-C SyncE and dynamic pin discovery
>
> From: Arkadiusz Kubalewski <[email protected]>
>
> Add DPLL support for the Intel E825-C Ethernet controller. Unlike
> previous generations (E810), the E825-C connects to the platform's
> DPLL subsystem via MUX pins defined in the system firmware (Device
> Tree/ACPI).
>
> Implement the following mechanisms to support this architecture:
>
> 1. Dynamic Pin Discovery: Use the fwnode_dpll_pin_find() helper to
> locate the parent MUX pins defined in the firmware.
>
> 2. Asynchronous Registration: Since the platform DPLL driver may probe
> independently of the network driver, utilize the DPLL notifier
> chain
> (register_dpll_notifier). The driver listens for DPLL_PIN_CREATED
> events to detect when the parent MUX pins become available, then
> registers its own Recovered Clock (RCLK) pins as children of those
> parents.
>
> 3. Hardware Configuration: Implement the specific register access
> logic
> for E825-C CGU (Clock Generation Unit) registers (R10, R11). This
> includes configuring the bypass MUXes and clock dividers required
> to
> drive SyncE signals.
>
> 4. Split Initialization: Refactor `ice_dpll_init()` to separate the
> static initialization path of E810 from the dynamic, firmware-
> driven
> path required for E825-C.
>
> Co-developed-by: Ivan Vecera <[email protected]>
> Signed-off-by: Ivan Vecera <[email protected]>
> Co-developed-by: Grzegorz Nitka <[email protected]>
> Signed-off-by: Grzegorz Nitka <[email protected]>
> Signed-off-by: Arkadiusz Kubalewski <[email protected]>
> ---
> drivers/net/ethernet/intel/ice/ice_dpll.c | 715 +++++++++++++++++--
> -
> drivers/net/ethernet/intel/ice/ice_dpll.h | 25 +
> drivers/net/ethernet/intel/ice/ice_lib.c | 3 +
> drivers/net/ethernet/intel/ice/ice_ptp.c | 29 +
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 9 +-
> drivers/net/ethernet/intel/ice/ice_tspll.c | 217 ++++++
> drivers/net/ethernet/intel/ice/ice_tspll.h | 13 +-
> drivers/net/ethernet/intel/ice/ice_type.h | 6 +
> 8 files changed, 925 insertions(+), 92 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c
> b/drivers/net/ethernet/intel/ice/ice_dpll.c
> index 4eca62688d834..06575d42de6e9 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dpll.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
> @@ -5,6 +5,7 @@
...
> +/**
> + * ice_dpll_init_fwnode_pins - initialize pins from device tree
> + * @pf: board private structure
> + * @pins: pointer to pins array
> + * @start_idx: starting index for pins
> + * @count: number of pins to initialize
> + *
> + * Initialize input pins for E825 RCLK support. The parent pins
> (rclk0,
> +rclk1)
> + * are expected to be defined in the device tree (ACPI). This
> function
> +allocates
Device Tree and ACPI are different firmware interfaces, aren't they?
Writing "device tree (ACPI)" can mislead readers about where the
fwnode-backed discovery is expected to come from.
The code looks good for me.
Reviewed-by: Aleksandr Loktionov <[email protected]>
> + * them in the dpll subsystem and stores their indices for later
> +registration
> + * with the rclk pin.
...
> --
> 2.52.0
