> -----Original Message-----
> From: Intel-wired-lan <[email protected]> On Behalf
> Of Vitaly Lifshits
> Sent: Tuesday, January 6, 2026 11:04 AM
> To: [email protected]
> Cc: Lifshits, Vitaly <[email protected]>
> Subject: [Intel-wired-lan] [PATCH iwl-next v2 1/1] e1000e: correct
> TIMINCA on ADP/TGP systems with wrong XTAL frequency
>
> On some Tiger Lake (TGP) and Alder Lake (ADP) platforms, the hardware
> XTAL clock is incorrectly interpreted as 24 MHz instead of the actual
> 38.4 MHz. This causes the PHC to run significantly faster than system
> time, breaking PTP synchronization.
>
> To mitigate this at runtime, measure PHC vs system time over ~1 ms
> using cross-timestamps. If the PHC increment differs from system time
> beyond the expected tolerance (currently >100 uSecs), reprogram
> TIMINCA for the
> 38.4 MHz profile and reinitialize the timecounter.
>
> Tested on an affected system using phc_ctl:
> Without fix:
> sudo phc_ctl enp0s31f6 set 0.0 wait 10 get clock time: 16.000541250
> (expected ~10s)
>
> With fix:
> sudo phc_ctl enp0s31f6 set 0.0 wait 10 get clock time: 9.984407212
> (expected ~10s)
>
> Signed-off-by: Vitaly Lifshits <[email protected]>
> ---
> v2: avoid resetting the systim and rephrase commit message
> v1: initial version
> ---
> drivers/net/ethernet/intel/e1000e/netdev.c | 80
> ++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c
> b/drivers/net/ethernet/intel/e1000e/netdev.c
> index 116f3c92b5bc..edb72054d0d9 100644
> --- a/drivers/net/ethernet/intel/e1000e/netdev.c
> +++ b/drivers/net/ethernet/intel/e1000e/netdev.c
> @@ -3904,6 +3904,83 @@ static void e1000_flush_desc_rings(struct
> e1000_adapter *adapter)
> e1000_flush_rx_ring(adapter);
> }
>
> +/**
> + * e1000e_xtal_tgp_workaround - Adjust XTAL clock based on PHC and
> +system
> + * clock delta.
> + *
> + * Measures the time difference between the PHC (Precision Hardware
> +Clock)
> + * and the system clock over a 1 millisecond interval. If the delta
> + * exceeds 100 microseconds, reconfigure the XTAL clock to 38.4 MHz.
> + *
> + * @adapter: Pointer to the private adapter structure **/ static
> void
> +e1000e_xtal_tgp_workaround(struct e1000_adapter *adapter) {
> + s64 phc_delta, sys_delta, sys_start_ns, sys_end_ns, delta_ns;
...
> /**
> * e1000e_systim_reset - reset the timesync registers after a
> hardware reset
> * @adapter: board private structure
> @@ -3955,6 +4032,9 @@ static void e1000e_systim_reset(struct
> e1000_adapter *adapter)
> if (extack._msg)
> e_err("%s\n", extack._msg);
> }
> +
> + if (hw->mac.type == e1000_pch_adp || hw->mac.type ==
> e1000_pch_tgp)
> + return e1000e_xtal_tgp_workaround(adapter);
Vitaly, does it compile? As far a can see the function is declared as void
> }
>
> /**
> --
> 2.34.1
