Dear Aleksandr, dear Paul,
Thank you for your patch. Some minor comments, should you resend.
Am 23.03.26 um 09:58 schrieb Aleksandr Loktionov:
From: Paul Greenwalt <[email protected]>
Update ice_link_mode_str_high() with strings for 200G PHY types.
Without these entries the ice_dump_phy_type() debug helper prints
nothing for phy_type_high bits [5..15], covering all 200G and
400GBASE-FR8 PHY types supported by E825C hardware.
How does the system need to be configured to get `ice_dump_phy_type()`
called?
Also, the commit message title just mentions 200G, but here you mention
400G too.
Also add the corresponding ICE_PHY_TYPE_HIGH_* bit definitions for
indices 13-15 (200G_AUI8_AOC_ACC, 200G_AUI8, 400GBASE_FR8) that were
missing from ice_adminq_cmd.h, and update ICE_PHY_TYPE_HIGH_MAX_INDEX
from 12 to 15. Without these definitions ice_get_phy_type_high() would
stop iterating at index 12, leaving the new PHY types invisible to all
code that bounds-checks against MAX_INDEX.
Maybe this should have been a separate commit, but it’s not important.
Fixes: none (new hardware support)
Signed-off-by: Paul Greenwalt <[email protected]>
Signed-off-by: Aleksandr Loktionov <[email protected]>
---
v1 -> v2 update ICE_PHY_TYPE_HIGH_MAX_INDEX
---
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h | 5 ++++-
drivers/net/ethernet/intel/ice/ice_common.c | 11 +++++++++++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
index 859e9c6..f64d2ef 100644
--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
@@ -1044,7 +1044,10 @@ struct ice_aqc_get_phy_caps {
#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10)
#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11)
#define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12)
-#define ICE_PHY_TYPE_HIGH_MAX_INDEX 12
+#define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC BIT_ULL(13)
+#define ICE_PHY_TYPE_HIGH_200G_AUI8 BIT_ULL(14)
+#define ICE_PHY_TYPE_HIGH_400GBASE_FR8 BIT_ULL(15)
+#define ICE_PHY_TYPE_HIGH_MAX_INDEX 15
struct ice_aqc_get_phy_caps_data {
__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c
b/drivers/net/ethernet/intel/ice/ice_common.c
index 2cebe4e..c6727c5 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -84,6 +84,17 @@ static const char * const ice_link_mode_str_high[] = {
[2] = "100G_CAUI2",
[3] = "100G_AUI2_AOC_ACC",
[4] = "100G_AUI2",
+ [5] = "200G_CR4_PAM4",
+ [6] = "200G_SR4",
+ [7] = "200G_FR4",
+ [8] = "200G_LR4",
+ [9] = "200G_DR4",
+ [10] = "200G_KR4_PAM4",
+ [11] = "200G_AUI4_AOC_ACC",
+ [12] = "200G_AUI4",
+ [13] = "200G_AUI8_AOC_ACC",
+ [14] = "200G_AUI8",
+ [15] = "400GBASE_FR8",
};
/**
Reviewed-by: Paul Menzel <[email protected]>
Kind regards,
Paul
