On 5/4/2026 7:24 AM, Aleksandr Loktionov wrote: > Three correctness fixes and two cleanups for the ice driver. > > Patch 1 corrects a kernel-doc comment in ice_ptp_hw.h that described the > ETH56G MAC Rx offset field as unsigned when it is signed (trivial doc fix, > no functional change). > > Patch 2 removes the PF_SB_REM_DEV_CTL sideband register write from > ice_ptp_init_phc_e82x(). PHY access is enabled by default on E82X and > the register write was a leftover from an earlier SWITCH_MODE workaround > that is no longer needed. > > Patch 3 renames ICE_SMA2_UFL2_RX_DIS to ICE_SMA2_UFL2_RX_EN to match > the actual active-high hardware semantics and inverts the three use sites > in ice_dpll.c so that the logic remains correct. > > Patch 4 replaces the static per-type frequency tables for CGU pins with a > single DPLL_PIN_FREQUENCY_RANGE(1, 25 MHz) entry. The firmware defines > an any_freq capability for configurable CGU inputs, but the old tables > restricted users to 1 PPS or 10 MHz. GNSS pins retain a 1 PPS-only > entry since they are physically constrained. > > Patch 5 exports ice_dcb_need_recfg() and calls it in the four SW LLDP > netlink setters instead of memcmp() on a non-packed struct, which is > undefined behaviour due to uninitialised padding bytes. The redundant > memcmp in ice_pf_dcb_cfg() is removed since callers now guard it. >
Some of these seem like they belong as net fixes, not cleanups targetting next. Specifically patch 3 and 4 I feel should be separated. Could you please either justify why those issues are not "fixes" worthy of net, or separate them into their own series? Thanks, Jake
