Use a pointer to the struct ice_dpll_pin to link multiplexed pins. This allows to simplify the selection logic.
Signed-off-by: Sergey Temerkhanov <[email protected]> Reviewed-by: Aleksandr Loktionov <[email protected]> Reviewed-by: Przemyslaw Korba <[email protected]> --- drivers/net/ethernet/intel/ice/ice_dpll.c | 60 +++++++++++------------ drivers/net/ethernet/intel/ice/ice_dpll.h | 1 + 2 files changed, 31 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c index 1ca137f67dd4..fed7c9fea953 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -544,6 +544,29 @@ ice_dpll_pin_disable(struct ice_hw *hw, struct ice_dpll_pin *pin, return ret; } +/** + * ice_dpll_sw_pin_notify_peer - notify the paired SW pin after a state change + * @changed: the SW pin that was explicitly changed (already notified by dpll core) + * + * SMA and U.FL pins share physical signal paths in pairs (SMA1/U.FL1 and + * SMA2/U.FL2). When one pin's routing changes via the PCA9575 GPIO + * expander, the paired pin's state may also change. Send a change + * notification for the peer pin so userspace consumers monitoring the + * peer via dpll netlink learn about the update. + * + * Context: Called from dpll_pin_ops callbacks after pf->dplls.lock is + * released. Uses __dpll_pin_change_ntf() because dpll_lock is + * still held by the dpll netlink layer. + */ +static void ice_dpll_sw_pin_notify_peer(struct ice_dpll_pin *changed) +{ + struct ice_dpll_pin *peer; + + peer = changed->muxed; + if (peer->pin) + __dpll_pin_change_ntf(peer->pin); +} + /** * ice_dpll_pin_store_state - updates the state of pin in SW bookkeeping * @pin: pointer to a pin @@ -1171,32 +1194,6 @@ ice_dpll_input_state_get(const struct dpll_pin *pin, void *pin_priv, extack, ICE_DPLL_PIN_TYPE_INPUT); } -/** - * ice_dpll_sw_pin_notify_peer - notify the paired SW pin after a state change - * @d: pointer to dplls struct - * @changed: the SW pin that was explicitly changed (already notified by dpll core) - * - * SMA and U.FL pins share physical signal paths in pairs (SMA1/U.FL1 and - * SMA2/U.FL2). When one pin's routing changes via the PCA9575 GPIO - * expander, the paired pin's state may also change. Send a change - * notification for the peer pin so userspace consumers monitoring the - * peer via dpll netlink learn about the update. - * - * Context: Called from dpll_pin_ops callbacks after pf->dplls.lock is - * released. Uses __dpll_pin_change_ntf() because dpll_lock is - * still held by the dpll netlink layer. - */ -static void ice_dpll_sw_pin_notify_peer(struct ice_dplls *d, - struct ice_dpll_pin *changed) -{ - struct ice_dpll_pin *peer; - - peer = (changed >= d->sma && changed < d->sma + ICE_DPLL_PIN_SW_NUM) ? - &d->ufl[changed->idx] : &d->sma[changed->idx]; - if (peer->pin) - __dpll_pin_change_ntf(peer->pin); -} - /** * ice_dpll_sma_direction_set - set direction of SMA pin * @p: pointer to a pin @@ -1258,7 +1255,7 @@ static int ice_dpll_sma_direction_set(struct ice_dpll_pin *p, * backing pin when U.FL becomes inactive because the SMA pin may * still be using it. */ - peer = &d->ufl[p->idx]; + peer = p->muxed; if (peer->active) { struct ice_dpll_pin *target; enum ice_dpll_pin_type type; @@ -1388,7 +1385,7 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, unlock: mutex_unlock(&pf->dplls.lock); if (!ret) - ice_dpll_sw_pin_notify_peer(&pf->dplls, p); + ice_dpll_sw_pin_notify_peer(p); return ret; } @@ -1508,7 +1505,7 @@ ice_dpll_sma_pin_state_set(const struct dpll_pin *pin, void *pin_priv, unlock: mutex_unlock(&pf->dplls.lock); if (!ret) - ice_dpll_sw_pin_notify_peer(&pf->dplls, sma); + ice_dpll_sw_pin_notify_peer(sma); return ret; } @@ -1705,7 +1702,7 @@ ice_dpll_pin_sma_direction_set(const struct dpll_pin *pin, void *pin_priv, ret = ice_dpll_sma_direction_set(p, direction, extack); mutex_unlock(&pf->dplls.lock); if (!ret) - ice_dpll_sw_pin_notify_peer(&pf->dplls, p); + ice_dpll_sw_pin_notify_peer(p); return ret; } @@ -4623,6 +4620,8 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) if (pin->input->ref_sync) pin->ref_sync = pin->input->ref_sync - pin_abs_idx; pin->output = &d->outputs[ICE_DPLL_PIN_SW_OUTPUT_ABS(i)]; + pin->muxed = &d->ufl[i]; + ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); } for (i = 0; i < ICE_DPLL_PIN_SW_NUM; i++) { @@ -4656,6 +4655,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | caps); } + pin->muxed = &d->sma[i]; ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); } diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.h b/drivers/net/ethernet/intel/ice/ice_dpll.h index c59d746a8567..c102ff2649d9 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.h +++ b/drivers/net/ethernet/intel/ice/ice_dpll.h @@ -78,6 +78,7 @@ struct ice_dpll_pin { s32 phase_adjust; struct ice_dpll_pin *input; struct ice_dpll_pin *output; + struct ice_dpll_pin *muxed; enum dpll_pin_direction direction; s64 phase_offset; u8 status; -- 2.53.0
