> -----Original Message----- > From: Keller, Jacob E <[email protected]> > Sent: Friday, August 21, 2026 5:13 PM > To: Intel Wired LAN <[email protected]> > Cc: [email protected]; Machnikowski, Maciej > <[email protected]>; Nguyen, Anthony L > <[email protected]>; Korba, Przemyslaw <[email protected]>; > Nitka, Grzegorz <[email protected]>; Oros, Petr <[email protected]>; > Nowlin, Alexander <[email protected]>; Bross, Kevin > <[email protected]>; Cavatur, Ranjit <[email protected]>; Keller, > Jacob E <[email protected]>; Machnikowski, Maciej > <[email protected]> > Subject: [PATCH iwl-net 05/12] ice: E825: stop clearing > PHY_REG_TX_OFFSET_READY > > The ice_stop_phy_timer_eth56g() function is called by the driver for E825 > devices to ensure that the PHY timer has been stopped. The equivalent > function for older E822 devices performed many steps. However, on E825 it > only clears the PHY_REG_TX_OFFSET_READY and PHY_REG_RX_OFFSET_READY bits to > indicate to HW that it should no longer treat the PHY offset as valid. > > When PHY_REG_TX_OFFSET_READY is cleared, the hardware still captures Tx > timestamps, but it no longer sets the valid bit for these timestamps. This > sounds reasonable at first glance. However, this results in the internal > outstanding timestamp counter becoming out of sync. > > When capturing a timestamp, hardware increments its internal counter and sets > the associated "ready" bit in the timestamp memory status. Then it compares > the timestamp count to the threshold to determine > if it should trigger an > interrupt to the MAC. > > Upon reading the timestamp hardware is supposed to decrement the counter, > clear the valid bit, and clear the associated bit from the memory status > register. However, it only performs these steps *if* the valid > bit is set. > > Since the valid bit is not set while PHY_REG_TX_OFFSET_READY is clear, the > timestamp counter is not decremented and the memory status is not cleared. > This leaves the counter out-of-sync until a PHY soft reset. > > According to the hardware engineers, the PHY_REG_TX_OFFSET_READY bit has no > other effects. It only controls whether hardware captures timestamps with the > valid bit set or not. Since capturing timestamps with the valid bit clear is > problematic, they recommend simply not clearing PHY_REG_TX_OFFSET_READY. > > Note that the PHY_REG_RX_OFFSET_READY performs a similar task. However, > clearing it is fine as there is no associated timestamp counter on the Rx > side. Receive timestamps are simply inserted into the descriptor. Clearing > this register clears the valid bit for timestamps until we complete > calibration and re-enable the register. > > Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products") > Suggested-by: Maciej Machnikowski <[email protected]> > Signed-off-by: Jacob Keller <[email protected]> > --- > drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 4 ---- > 1 file changed, 4 deletions(-)
Tested-by: Alexander Nowlin <[email protected]>
