> -----Original Message-----
> From: Petr Oros <[email protected]>
> Sent: Thursday, September 17, 2026 12:03 PM
> To: [email protected]
> Cc: Oros, Petr <[email protected]>; Nguyen, Anthony L
> <[email protected]>; Kitszel, Przemyslaw
> <[email protected]>; Andrew Lunn <[email protected]>; David S.
> Miller <[email protected]>; Eric Dumazet <[email protected]>; Jakub
> Kicinski <[email protected]>; Paolo Abeni <[email protected]>; Simon Horman
> <[email protected]>; Kubalewski, Arkadiusz <[email protected]>;
> [email protected]; [email protected]
> Subject: [PATCH iwl-net 2/2] ice: skip the SW pin description on boards with
> generic DPLL pins
>
> ice_dpll_init_info_sw_pins() describes the SMA and U.FL wrappers by pointing
> them at fixed positions of the input and output arrays, inputs
> 4 and 5 and outputs 0 and 1 on an E810-C SFP, and reads the ref-sync partner
> of the input it picked. The arrays are sized by the pin counts firmware
> reports. On a board that does not match the Intel reference layout the driver
> has already fallen back to generic pins, and when such a board reports fewer
> pins than the reference the reads run past the end of the arrays.
>
> The wrappers are never registered on a generic board, but
> ice_dpll_init_pins() still calls ice_dpll_pin_ref_sync_register() on them, so
> a stray nonzero partner from the out of bounds read would pair NULL pins.
>
> Describe the wrappers only when the static pin table is in use and keep their
> ref-sync registration under the same condition. The default programming of
> the PCA9575 clock mux stays on the generic path, a board that has the mux
> still needs its SMA connectors switched to inputs.
>
> Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
> Signed-off-by: Petr Oros <[email protected]>
> ---
> drivers/net/ethernet/intel/ice/ice_dpll.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
Tested-by: Alexander Nowlin <[email protected]>
