> -----Original Message----- > From: Petr Oros <[email protected]> > Sent: Thursday, September 17, 2026 12:04 PM > To: [email protected] > Cc: Oros, Petr <[email protected]>; Nguyen, Anthony L > <[email protected]>; Kitszel, Przemyslaw > <[email protected]>; Andrew Lunn <[email protected]>; David S. > Miller <[email protected]>; Eric Dumazet <[email protected]>; Jakub > Kicinski <[email protected]>; Paolo Abeni <[email protected]>; Simon Horman > <[email protected]>; Kubalewski, Arkadiusz <[email protected]>; > [email protected]; [email protected] > Subject: [PATCH iwl-next] ice: describe generic DPLL pins from firmware pin > classification > > When the number of CGU pins reported by firmware does not match the static > pin table for the device, the driver falls back to the generic pins added by > commit 6e58c33106220c ("ice: fix crash on probe for DPLL enabled E810 LOM"), > named "0" to "15". The same labels are used for inputs and outputs, so a > PIN_ID_GET lookup by board label fails with "multiple matches" for any index > present on both sides and userspace such as synce4l cannot address the pin at > all. The pin type is guessed from the current frequency and no supported > frequency list is exposed. > > Firmware already classifies every input pin. Get CGU Input Config > (0x0C63) returns a type field marking GPS, PHY recovered clock and external > inputs, and a capability field with the supported 1PPS and > 10 MHz frequencies. The driver discards both, ice_dpll_pin_state_update() > passes NULL for them. > > Use them in the generic path. Inputs become GNSS-<n>, RCLK-<n>, EXT-<n>, or > IN-<n> when firmware reports no kind, with the matching dpll pin type and > frequency list. An external input flagged as accepting any frequency > advertises the standard 1PPS and 10 MHz pair. Outputs become OUT-<n>. > Labels are unique across both directions and the 16 pin limit, which existed > only because of the static label table, is gone. Labels that happened to be > unique before, indexes above the smaller of the two pin counts, change as > well. > > On an E810-C timing board firmware reports the C827 recovered clock inputs as > PHY, the SMA inputs as external with 1PPS and 10 MHz, and the GNSS input as > GPS with 1PPS, matching the static table for that board. > A vendor board with 8 inputs and 15 outputs, which takes the generic path > today, gets addressable and correctly typed pins instead of ambiguous > numbers. The DPLL registration on such boards is fixed by > "ice: DPLL init fixes for E810 timing boards" on iwl-net, this patch is > independent of it. > > Signed-off-by: Petr Oros <[email protected]> > --- > drivers/net/ethernet/intel/ice/ice_dpll.c | 72 +++++++++++++++++---- > drivers/net/ethernet/intel/ice/ice_dpll.h | 2 + > drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 31 +++++++++ > drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 2 + > 4 files changed, 95 insertions(+), 12 deletions(-)
Tested-by: Alexander Nowlin <[email protected]>
