dpll_lock protects topology and object lifetime, but it also serializes all driver callbacks in the system, so one slow device stalls every other DPLL device, whichever driver it belongs to. mlx5 callbacks issue firmware commands with a 60 s default timeout, and zl3073x callbacks can wait seconds on a driver lock held across ToD writes and phase steps.
Make dpll_lock an rwsem for topology and lifetime and add a mutex per domain for callbacks. A domain is all objects created with one (module, clock_id), in practice one chip or card, so channels of one chip stay serialized as drivers expect, and they still block each other. Device callbacks run under the domain of the device, pin callbacks under the domain of the pin, whichever driver registered them. Only one domain lock is ever held, so domains have no lock order. A lock per device would not work, because pins are N:M with devices and callbacks notify sibling channels. The driver API does not change, but a callback can now notify only objects of its own domain. Patch 1 changes the one in-tree callback that does not follow this. Registrations across domains exist in the tree only on E825, where ice registers fwnode pins of an external DPLL with its TXC and TSPLL DPLLs. These callbacks are no longer serialized with TXC and TSPLL, they rely on pf->dplls.lock, and requests about these pins wait while the external DPLL is busy. Intel folks, please check that this is fine. Each complex of a dual complex E825 has its own DSN and so its own domain, but both use the CGU of complex 0. Patch 2 adds a lock for the registers they share. Without it a test lost updates of them. Patch 5 is the only patch that lets callbacks run concurrently. Patch 6 adds KUnit tests. I also tested each commit with a mock driver and YNL in QEMU, with lockdep and KASAN, and the tip with lockdep on two systems: - A board with ZL30732A: every notification the driver sends from a callback, concurrent traffic with PTP, driver reload and rebind. - GNR-D with dual complex E825 and zl3073x: callbacks of the pins shared by both drivers, TX clock switches, RCLK pins of both complexes, a port going down and up, and both drivers unloaded and loaded in either order under load. mlx5 is build tested only. On GNR-D, with ToD writes running on the zl3073x and requests waiting for them, requests to an ice DPLL took 1448 ms in median and 3.9 s at most before this series, 0.2 ms and 0.3 ms with it, the same as when idle. Requests about the pins shared by both drivers still wait for the zl3073x. Ivan Vecera (10): ice: dpll: notify TSPLL lock status from the periodic work only ice: dpll: serialize changes of the SyncE CGU registers dpll: add domain object dpll: take domain locks around driver callbacks dpll: convert dpll_lock to rwsem dpll: add KUnit tests for core locking dpll: reject measured_freq_get for foreign and on-pin registrations dpll: zl3073x: update locking comments ice: dpll: update locking comments dpll: document locking rules Documentation/driver-api/dpll.rst | 44 + drivers/dpll/.kunitconfig | 5 + drivers/dpll/Kconfig | 13 + drivers/dpll/Makefile | 1 + drivers/dpll/dpll_core.c | 187 ++- drivers/dpll/dpll_core.h | 34 +- drivers/dpll/dpll_core_kunit.c | 1573 ++++++++++++++++++ drivers/dpll/dpll_netlink.c | 117 +- drivers/dpll/zl3073x/dpll.c | 9 +- drivers/net/ethernet/intel/ice/ice_adapter.c | 2 + drivers/net/ethernet/intel/ice/ice_adapter.h | 4 + drivers/net/ethernet/intel/ice/ice_dpll.c | 29 +- drivers/net/ethernet/intel/ice/ice_dpll.h | 7 + drivers/net/ethernet/intel/ice/ice_ptp.c | 2 + drivers/net/ethernet/intel/ice/ice_tspll.c | 4 +- 15 files changed, 1915 insertions(+), 116 deletions(-) create mode 100644 drivers/dpll/.kunitconfig create mode 100644 drivers/dpll/dpll_core_kunit.c base-commit: 6584acd42820478910a771efb28a355a707e9cb0 -- 2.56.0
