Do you have an ability to scope the 5V rail and possibly the USB VBUS rail? Would be interesting to see whether the drops are possibly associated with voltage sags resulting from high current (either continuous or transient). Also, if you look at the schematic, you'll notice the resettable fuse F1, which adds some additional series resistance on the VBUS rail causing additional sagging. Really, the IOIO was designed with the standard 500mA in mind, but if you bypass (short) this fuse I see no reason why you shouldn't be able to exceed that. And I wouldn't recommend you to use an external regulator, unless you have an actual reason to believe that the on-board one is problematic. The current limiting circuit should not add significant ESR I believe (assuming the pot is fully-clockwise, of course).
On Tue, Feb 23, 2016 at 12:40 AM, James Warner <[email protected]> wrote: > Ytai - still struggling with this, it's the last piece in the project > working! > > Really keen to work with you to implement a watchdog reset in case the USB > locks up at the IOIO end - I'm not skilled coding for PICs but happy to > assist in any other way > > James > > -- > You received this message because you are subscribed to the Google Groups > "ioio-users" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > To post to this group, send email to [email protected]. > Visit this group at https://groups.google.com/group/ioio-users. > For more options, visit https://groups.google.com/d/optout. > -- You received this message because you are subscribed to the Google Groups "ioio-users" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at https://groups.google.com/group/ioio-users. For more options, visit https://groups.google.com/d/optout.
