Stephen Warren <[email protected]> wrote @ Tue, 29 Jan 2013 18:03:51 +0100:
> > + /* Same as "mc" 1st regiter block start address */
> > + smmu->regbase = (void __iomem *)((u32)smmu->regs[0] & ~PAGE_MASK);
>
> I'm not sure if it's relevant how these register ranges are related to
> the MC registers, given this is the SMMU driver?
All SMMU register offsets are against MC[0]'s start address and SMMU
register blocks are interleaved as below. The 1st SMMU register block
SMMU[0]'s offset is always 0x10.
Address Register block
-----------------------
000-010 MC[0]
010-03c SMMU[0]
03c-1f0 MC[1]
1f0-200 SMMU[1]
200-228 MC[2]
228-284 SMMU[2]
284-... MC[3]
If the above assumption is not acceptable, alternatively we need to
access MC's node to get the 1st MC register block start address, for
example, via embedded in MC's phandle in smmu entry.
Modified arch/arm/boot/dts/tegra30.dtsi
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index c5db29d..e9fb9ef 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -397,7 +397,7 @@
reg = <0x7000e400 0x400>;
};
- memory-controller {
+ mc: memory-controller {
compatible = "nvidia,tegra30-mc";
reg = <0x7000f000 0x010
0x7000f03c 0x1b4
@@ -414,6 +414,7 @@
nvidia,#asids = <4>; /* # of ASIDs */
dma-window = <0 0x40000000>; /* IOVA start & length */
nvidia,ahb = <&ahb>;
+ nvidia.mc = <&mc>;
};
ahub {
I may think that above may be a bit too much since we know that the
1st SMMU offset(0x10) and also that the MC register is aligned with
page boundary, and the following works actually.
smmu->regbase = (void __iomem *)((u32)smmu->regs[0] & ~PAGE_MASK);
I don't think that the existing SMMU/MC register offsets will change so easily.
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