On Wed, Sep 24 2014 at 09:37:12 AM, Will Deacon <[email protected]> wrote: > On Wed, Sep 24, 2014 at 02:12:00AM +0100, Mitchel Humpherys wrote: >> On Mon, Sep 22 2014 at 08:26:14 AM, Will Deacon <[email protected]> wrote: >> > On Thu, Sep 11, 2014 at 07:30:44PM +0100, Mitchel Humpherys wrote: >> >> + return arm_smmu_iova_to_phys_soft(domain, iova); >> >> + } >> >> + >> >> + phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO); >> >> + phys |= ((u64) readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32; >> >> + >> >> + if (phys & CB_PAR_F) { >> >> + dev_err(dev, "translation fault on %s!\n", dev_name(dev)); >> >> + dev_err(dev, "PAR = 0x%llx\n", phys); >> >> + } >> >> + phys = (phys & 0xFFFFFFF000ULL) | (iova & 0x00000FFF); >> > >> > How does this work for 64k pages? >> >> So at the moment we're always assuming that we're using v7/v8 long >> descriptor format, right? All I see in the spec (14.5.15 SMMU_CBn_PAR) >> is that bits[47:12]=>PA[47:12]... Or am I missing something completely? > > I think you've got 64k pages confused with the short-descriptor format. > > When we use 64k pages with long descriptors, you're masked off bits 15-12 of > the iova above, so you'll have a hole in the physical address afaict.
Even with long descriptors the spec says bits 15-12 should come from CB_PAR... It makes no mention of reinterpreting those bits depending on the programmed page granule. The only thing I can conclude from the spec is that hardware should be smart enough to do the right thing with bits 15-12 when the page granule is 64k. Although even if hardware is smart enough I guess CB_PAR[15:12] should be the same as iova[15:12] for the 64k case? -Mitch -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
