This flag is used for specifying access to device memory. SMMU would apply device memory attributes for a DMA transaction. This is required for setting access to GIC registers, for generating message interrupts. This would ensure that transactions targetting device memory are not gathered or reordered.
Signed-off-by: Varun Sethi <[email protected]> --- drivers/iommu/arm-smmu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index ca18d6d..f8338d6 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1263,6 +1263,10 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd, if (prot & IOMMU_CACHE) pteval |= (MAIR_ATTR_IDX_CACHE << ARM_SMMU_PTE_ATTRINDX_SHIFT); + + if (prot & IOMMU_DEVICE) + pteval |= (MAIR_ATTR_IDX_DEV << + ARM_SMMU_PTE_ATTRINDX_SHIFT); } else { pteval |= ARM_SMMU_PTE_HAP_FAULT; if (prot & IOMMU_READ) @@ -1273,6 +1277,9 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd, pteval |= ARM_SMMU_PTE_MEMATTR_OIWB; else pteval |= ARM_SMMU_PTE_MEMATTR_NC; + + if (prot & IOMMU_DEVICE) + pteval |= ARM_SMMU_PTE_MEMATTR_DEV; } /* If no access, create a faulting entry to avoid TLB fills */ -- 1.7.9.5 _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
