2015-01-20 23:04+0200, Nadav Amit: > Radim Kr?má? <rkrc...@redhat.com> wrote: > > 2015-01-14 01:27+0000, Wu, Feng: > >>> the new > >>>> hardware even doesn't consider the TPR for lowest priority interrupts > >>> delivery. > >>> > >>> A bold move ... what hardware was the first to do so? > >> > >> I think it was starting with Nehalem. > > > > Thanks, (Could be that QPI can't inform about TPR changes anymore ...) > > > > I played with Linux's TPR on Haswell and found that is has no effect. > > Sorry for jumping into the discussion, but doesn’t it depend on > IA32_MISC_ENABLE[23]? This bit disables xTPR messages. On my machine it is > set (probably by the BIOS), but since there is no IA32_MISC_ENABLE is not > locked for changes, the OS can control it.
Thanks, I didn't know about it. On Ivy Bridge EP (the only modern machine at hand), the bit was set by default. After clearing it, TPR still had no effect. The most relevant mention of xTPR I found is related to FSB [1]. [2] isn't enlightening, so there might be more from QPI-era ... --- 1: Intel® E7320 Memory Controller Hub (MCH) Datasheet http://www.intel.com/content/dam/doc/datasheet/e7320-memory-controller-hub-datasheet.pdf 5.2.2 System Bus Interrupts 2: Intel® Xeon® Processor E5 v2 Family: Datasheet, Vol. 2 http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v2-datasheet-vol-2.pdf 6.1.2 IntControl _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
