This patch adds the device tree binding information for X-Gene AHBC IOMMU driver.
Signed-off-by: Suman Tripathi <[email protected]> --- .../devicetree/bindings/iommu/xgene,ahbc-iommu.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/xgene,ahbc-iommu.txt diff --git a/Documentation/devicetree/bindings/iommu/xgene,ahbc-iommu.txt b/Documentation/devicetree/bindings/iommu/xgene,ahbc-iommu.txt new file mode 100644 index 0000000..37ad3a6 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/xgene,ahbc-iommu.txt @@ -0,0 +1,31 @@ +*APM X-Gene AHBC IOMMU Architecture Implementation + +APM X-Gene SoC AHBC IOMMU translates the AHBC 32-bit address from +dma master to 42-bit AXI address by using a set of AIM(AHB Inbound mapper) +register. + +** AHBC IOMMU required properties: + +- compatible : Should be "apm,xgene-ahbc-iommu" +- reg : Base address of the AHBC AXI mapper registers +- iommu-cells : It is single master IOMMU. + +Example: + /* IOMMU controller device node */ + ahbc_iommu: ahbc_iommu@0x1f2a0080 { + compatible = "apm,xgene-ahbc-iommu"; + #iommu-cells = <0>; + reg = <0x0 0x1f2a0080 0x0 0x90>; + }; + + /* Master node */ + sdhc0: sdhc@1c000000 { + device_type = "sdhc"; + compatible = "arasan,sdhci-8.9a"; + reg = <0x0 0x1c000000 0x0 0x100>; + interrupts = <0x0 0x49 0x4>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&sdioclk 0>, <&ahbclk 0>; + iommus = <&ahbc_iommu>; + }; + -- 1.8.2.1 _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
