From: Jeremy Gebben <[email protected]> In the ARM SMMU architecture, pagetable programming is controlled by the TTBR0 register. The layout of this registers varies depending on the pagetable format in use. In particular, the ASID (address space ID) field is found in CONTEXTIDR when using V7S format and in the top bits of TTBR0 for V7L and V8L.
Some drivers need to program hardware to switch domains on the fly. This attribute allows the correct setting to be determined by querying the domain rather than directly reading registers and making assumptions about the pagetable format. The domain must be attached before TTBR0 may be queried. Signed-off-by: Jeremy Gebben <[email protected]> Signed-off-by: Jordan Crouse <[email protected]> --- include/linux/iommu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index d537cc9..544cfc6 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -115,6 +115,7 @@ enum iommu_attr { DOMAIN_ATTR_FSL_PAMUV1, DOMAIN_ATTR_NESTING, /* two stages of translation */ DOMAIN_ATTR_ENABLE_TTBR1, + DOMAIN_ATTR_TTBR0, DOMAIN_ATTR_MAX, }; -- 1.9.1 _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
