On 05.05.17 17:38:05, Geetha sowjanya wrote: > From: Linu Cherian <linu.cher...@cavium.com> > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > and PAGE0_REGS_ONLY option will be enabled as an errata workaround. > > This option when turned on, replaces all page 1 offsets used for > EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets. > > Signed-off-by: Linu Cherian <linu.cher...@cavium.com> > Signed-off-by: Geetha Sowjanya <geethasowjanya.ak...@cavium.com> > --- > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 +++ > drivers/iommu/arm-smmu-v3.c | 44 > ++++++++++++++++------ > 2 files changed, 38 insertions(+), 12 deletions(-)
> @@ -412,6 +412,9 @@ > #define MSI_IOVA_BASE 0x8000000 > #define MSI_IOVA_LENGTH 0x100000 > > +#define ARM_SMMU_PAGE0_REGS_ONLY(smmu) \ > + ((smmu)->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY) Why hide the check behind this macro? Maybe make ARM_SMMU_OPT_PAGE0_REGS_ONLY shorter a bit instead? -Robert _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
