On Tue, Jun 20, 2017 at 07:47:38PM +0530, Geetha sowjanya wrote: > From: Linu Cherian <linu.cher...@cavium.com> > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > and PAGE0_REGS_ONLY option is enabled as an errata workaround. > This option when turned on, replaces all page 1 offsets used for > EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets. > > SMMU resource size checks are now based on SMMU option PAGE0_REGS_ONLY, > since resource size can be either 64k/128k. > For this, arm_smmu_device_dt_probe/acpi_probe has been moved before > platform_get_resource call, so that SMMU options are set beforehand. > > Signed-off-by: Linu Cherian <linu.cher...@cavium.com> > Signed-off-by: Geetha Sowjanya <geethasowjanya.ak...@cavium.com> > --- > Documentation/arm64/silicon-errata.txt | 1 + > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 ++ > drivers/iommu/arm-smmu-v3.c | 68 ++++++++++++++----- > 3 files changed, 57 insertions(+), 18 deletions(-) > > diff --git a/Documentation/arm64/silicon-errata.txt > b/Documentation/arm64/silicon-errata.txt > index 10f2ddd..4693a32 100644 > --- a/Documentation/arm64/silicon-errata.txt > +++ b/Documentation/arm64/silicon-errata.txt > @@ -62,6 +62,7 @@ stable kernels. > | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 > | > | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 > | > | Cavium | ThunderX SMMUv2 | #27704 | N/A > | > +| Cavium | ThunderX2 SMMUv3| #74 | N/A > | > | | | | > | > | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 > | > | | | | > | > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt > b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt > index be57550..6ecc48c 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt > @@ -49,6 +49,12 @@ the PCIe specification. > - hisilicon,broken-prefetch-cmd > : Avoid sending CMD_PREFETCH_* commands to the SMMU. > > +- cavium,cn9900-broken-page1-regspace > + : Replaces all page 1 offsets used for EVTQ_PROD/CONS, > + PRIQ_PROD/CONS register access with page 0 offsets. > + Set for Caviun ThunderX2 silicon that doesn't support
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