Current 64-bit RISC-V cores don't have any iommu support, so they need
iommu support when used with more than 4GB DRAM (or even just address
space depending on the SBI). This wires the support up based on
earlier patches from Palmer.
Note that the patches are on to of the dma mapping tree as they require
the swiotlb Kconfig consolidation, and should probably merged through
that tree as well.
Git tree:
git://git.infradead.org/users/hch/misc.git riscv-swiotlb
Gitweb:
http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/riscv-swiotlb
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