On 2/12/19 11:02 AM, Peter Xu wrote:
On Tue, Feb 12, 2019 at 10:44:23AM +0800, Lu Baolu wrote:
Hi,
On 2/12/19 3:28 AM, Matthew Wilcox wrote:
I'm looking at commit 562831747f6299abd481b5b00bd4fa19d5c8a259
which fails to adequately explain why we can't use PASID 0. Commit
af39507305fb83a5d3c475c2851f4d59545d8a18 also doesn't explain why PASID
0 is no longer usable for the intel-svm driver.
Sorry that we didn't make it clear.
There are a load of simplifications that could be made to this, but I
don't know which ones to suggest without a clear understanding of the
problem you're actually trying to solve.
PASID 0 has been reserved by Intel IOMMU driver for RID_PASID purpose.
VT-d scalable mode treats all address translation as PASID granularity.
For DMA requests-with-PASID, the PASID value in the DMA request will be
used. For DMA requests-without-PASID, VT-d will use a static PASID value
specified in the RID_PASID field of the context entry. PASID 0 has been
reserved for this usage for all devices.
(Please refer to 9.4 of the spec 3.0 for more details.)
Hi, Baolu,
Hi Peter,
I have a similar confusion.
If PASID==0 is reserved for requests-without-PASID, then does it mean
that for each scalable mode context entry the RID_PASID field will
always be zero?
Yes.
Or say, since we already have the per-context-entry
RID_PASID field which seems to be configurable, why we still need to
reserve the PASID==0?
We decided to set RID_PASID always to 0. This will make things simple
especially for virtual IOMMU case. It will also be compatible with other
arch's which reserves PASID 0 for legacy translation.
Best regards,
Lu Baolu
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