On Fri, Aug 09, 2019 at 06:07:38PM +0100, Robin Murphy wrote:
> FIELD_PREP remains a terrible name, but the overall simplification will
> make further work on this stuff that much more manageable. This also
> serves as an audit of the header, wherein we can impose a consistent
> grouping and ordering of the offset and field definitions
> 
> Signed-off-by: Robin Murphy <robin.mur...@arm.com>
> ---
>  drivers/iommu/arm-smmu-regs.h | 126 ++++++++++++++++------------------
>  drivers/iommu/arm-smmu.c      |  51 +++++++-------
>  2 files changed, 84 insertions(+), 93 deletions(-)
> 
> diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h
> index 1c278f7ae888..d189f025537a 100644
> --- a/drivers/iommu/arm-smmu-regs.h
> +++ b/drivers/iommu/arm-smmu-regs.h
> @@ -10,111 +10,101 @@
>  #ifndef _ARM_SMMU_REGS_H
>  #define _ARM_SMMU_REGS_H
>  
> +#include <linux/bits.h>
> +
>  /* Configuration registers */
>  #define ARM_SMMU_GR0_sCR0            0x0
> -#define sCR0_CLIENTPD                        (1 << 0)
> -#define sCR0_GFRE                    (1 << 1)
> -#define sCR0_GFIE                    (1 << 2)
> -#define sCR0_EXIDENABLE                      (1 << 3)
> -#define sCR0_GCFGFRE                 (1 << 4)
> -#define sCR0_GCFGFIE                 (1 << 5)
> -#define sCR0_USFCFG                  (1 << 10)
> -#define sCR0_VMIDPNE                 (1 << 11)
> -#define sCR0_PTM                     (1 << 12)
> -#define sCR0_FB                              (1 << 13)
> -#define sCR0_VMID16EN                        (1 << 31)
> -#define sCR0_BSU_SHIFT                       14
> -#define sCR0_BSU_MASK                        0x3
> +#define sCR0_VMID16EN                        BIT(31)
> +#define sCR0_BSU                     GENMASK(15, 14)
> +#define sCR0_FB                              BIT(13)
> +#define sCR0_PTM                     BIT(12)
> +#define sCR0_VMIDPNE                 BIT(11)
> +#define sCR0_USFCFG                  BIT(10)
> +#define sCR0_GCFGFIE                 BIT(5)
> +#define sCR0_GCFGFRE                 BIT(4)
> +#define sCR0_EXIDENABLE                      BIT(3)
> +#define sCR0_GFIE                    BIT(2)
> +#define sCR0_GFRE                    BIT(1)
> +#define sCR0_CLIENTPD                        BIT(0)
>  
>  /* Auxiliary Configuration register */
>  #define ARM_SMMU_GR0_sACR            0x10
>  
>  /* Identification registers */
>  #define ARM_SMMU_GR0_ID0             0x20
> +#define ID0_S1TS                     BIT(30)
> +#define ID0_S2TS                     BIT(29)
> +#define ID0_NTS                              BIT(28)
> +#define ID0_SMS                              BIT(27)
> +#define ID0_ATOSNS                   BIT(26)
> +#define ID0_PTFS_NO_AARCH32          BIT(25)
> +#define ID0_PTFS_NO_AARCH32S         BIT(24)
> +#define ID0_CTTW                     BIT(14)
> +#define ID0_NUMIRPT                  GENMASK(23, 16)

nit: assuming this should be above ID0_CTTW so things are in descending
bit order?

Other than that, looks good to me.

Will
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