On 13/09/2019 15:35, Qian Cai wrote:
On Fri, 2019-09-13 at 12:48 +0100, Robin Murphy wrote:
Although CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is a welcome tool
for smoking out inadequate firmware, the failure mode is non-obvious
and can be confusing for end users. Add some special-case reporting of
Unidentified Stream Faults to help clarify this particular symptom.

CC: Douglas Anderson <[email protected]>
Signed-off-by: Robin Murphy <[email protected]>
---
  drivers/iommu/arm-smmu.c | 5 +++++
  drivers/iommu/arm-smmu.h | 2 ++
  2 files changed, 7 insertions(+)

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index b7cf24402a94..76ac8c180695 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -499,6 +499,11 @@ static irqreturn_t arm_smmu_global_fault(int irq, void 
*dev)
        dev_err_ratelimited(smmu->dev,
                "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 
0x%08x\n",
                gfsr, gfsynr0, gfsynr1, gfsynr2);
+       if (IS_ENABLED(CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT) &&
+           (gfsr & sGFSR_USF))
+               dev_err_ratelimited(smmu->dev,
+                       "Stream ID %hu may not be described by firmware, try booting with 
\"arm-smmu.disable_bypass=0\"\n",
+                       (u16)gfsynr1);

dev_err_once(), i.e., don't need to remind people to set "arm-
smmu.disable_bypass=0" multiple times.

Indeed, but in many cases it then quickly gets buried by an unending storm of repeated faults (not every console has capture and scrollback...)

Given that it's a "this is why your machine is on fire" kind of message, I figured that it's probably best to err on the side of visibility.

Robin.

arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, gfsr);
        return IRQ_HANDLED;
diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index c9c13b5785f2..46f7e161e83e 100644
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h
@@ -79,6 +79,8 @@
  #define ID7_MINOR                     GENMASK(3, 0)
#define ARM_SMMU_GR0_sGFSR 0x48
+#define sGFSR_USF                      BIT(2)
+
  #define ARM_SMMU_GR0_sGFSYNR0         0x50
  #define ARM_SMMU_GR0_sGFSYNR1         0x54
  #define ARM_SMMU_GR0_sGFSYNR2         0x58
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