> -----Original Message-----
> From: linux-kernel-ow...@vger.kernel.org <linux-kernel-
> ow...@vger.kernel.org> On Behalf Of Will Deacon
> Sent: Monday, September 16, 2019 11:48 PM
> To: Anup Patel <anup.pa...@wdc.com>
> Cc: Palmer Dabbelt <pal...@sifive.com>; guo...@kernel.org; Will Deacon
> <will.dea...@arm.com>; julien.thie...@arm.com; a...@eecs.berkeley.edu;
> james.mo...@arm.com; Arnd Bergmann <a...@arndb.de>;
> suzuki.poul...@arm.com; marc.zyng...@arm.com;
> catalin.mari...@arm.com; linux-ker...@vger.kernel.org;
> r...@linux.ibm.com; Christoph Hellwig <h...@infradead.org>; Atish Patra
> <atish.pa...@wdc.com>; julien.gr...@arm.com; g...@garyguo.net; Paul
> Walmsley <paul.walms...@sifive.com>; christoffer.d...@arm.com; linux-
> ri...@lists.infradead.org; kvm...@lists.cs.columbia.edu; linux-arm-
> ker...@lists.infradead.org; iommu@lists.linux-foundation.org
> Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a
> separate file
>
> On Sun, Sep 15, 2019 at 05:03:38AM +0000, Anup Patel wrote:
> >
> >
> > > -----Original Message-----
> > > From: linux-kernel-ow...@vger.kernel.org <linux-kernel-
> > > ow...@vger.kernel.org> On Behalf Of Palmer Dabbelt
> > > Sent: Saturday, September 14, 2019 7:31 PM
> > > To: w...@kernel.org
> > > Cc: guo...@kernel.org; Will Deacon <will.dea...@arm.com>;
> > > julien.thie...@arm.com; a...@eecs.berkeley.edu;
> james.mo...@arm.com;
> > > Arnd Bergmann <a...@arndb.de>; suzuki.poul...@arm.com;
> > > marc.zyng...@arm.com; catalin.mari...@arm.com; Anup Patel
> > > <anup.pa...@wdc.com>; linux-ker...@vger.kernel.org;
> > > r...@linux.ibm.com; Christoph Hellwig <h...@infradead.org>; Atish
> > > Patra <atish.pa...@wdc.com>; julien.gr...@arm.com; g...@garyguo.net;
> > > Paul Walmsley <paul.walms...@sifive.com>; christoffer.d...@arm.com;
> > > linux- ri...@lists.infradead.org; kvm...@lists.cs.columbia.edu;
> > > linux-arm- ker...@lists.infradead.org;
> > > iommu@lists.linux-foundation.org
> > > Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code
> > > in a separate file
> > >
> > > On Thu, 12 Sep 2019 07:02:56 PDT (-0700), w...@kernel.org wrote:
> > > > On Sun, Sep 08, 2019 at 07:52:55AM +0800, Guo Ren wrote:
> > > >> On Mon, Jun 24, 2019 at 6:40 PM Will Deacon <w...@kernel.org>
> wrote:
> > > >> > > I'll keep my system use the same ASID for SMP + IOMMU :P
> > > >> >
> > > >> > You will want a separate allocator for that:
> > > >> >
> > > >> > https://lkml.kernel.org/r/20190610184714.6786-2-jean-philippe.b
> > > >> > ruck
> > > >> > e...@arm.com
> > > >>
> > > >> Yes, it is hard to maintain ASID between IOMMU and CPUMMU or
> > > >> different system, because it's difficult to synchronize the
> > > >> IO_ASID when the CPU ASID is rollover.
> > > >> But we could still use hardware broadcast TLB invalidation
> > > >> instruction to uniformly manage the ASID and IO_ASID, or
> > > >> OTHER_ASID in
> > > our IOMMU.
> > > >
> > > > That's probably a bad idea, because you'll likely stall execution
> > > > on the CPU until the IOTLB has completed invalidation. In the case
> > > > of ATS, I think an endpoint ATC is permitted to take over a minute
> > > > to respond. In reality, I suspect the worst you'll ever see would
> > > > be in the msec range, but that's still an unacceptable period of
> > > > time to hold a
> > > CPU.
> > > >
> > > >> Welcome to join our disscusion:
> > > >> "Introduce an implementation of IOMMU in linux-riscv"
> > > >> 9 Sep 2019, 10:45 Jade-room-I&II (Corinthia Hotel Lisbon) RISC-V
> > > >> MC
> > > >
> > > > I attended this session, but it unfortunately raised many more
> > > > questions than it answered.
> > >
> > > Ya, we're a long way from figuring this out.
> >
> > For everyone's reference, here is our first attempt at RISC-V ASID
> > allocator:
> > http://archive.lwn.net:8080/linux-kernel/20190329045111.14040-1-anup.p
> > a...@wdc.com/T/#u
>
> With a reply stating that the patch "absolutely does not work" ;)
This patch was tested on existing HW (which does not have ASID implementation)
and tested on QEMU (which has very simplistic Implementation of ASID).
When I asked Gary Guo about way to get access to their HW (in same patch
email thread), I did not get any reply. After so many months passed, I now
doubt the his comment "absolutely does not work".
>
> What exactly do you want people to do with that? It's an awful lot of effort
> to
> review this sort of stuff and given that Guo Ren is talking about sharing page
> tables between the CPU and an accelerator, maybe you're better off
> stabilising Linux for the platforms that you can actually test rather than
> getting so far ahead of yourselves that you end up with a bunch of wasted
> work on patches that probably won't get merged any time soon.
The intention of the ASID patch was to encourage RISC-V implementations
having ASID in HW and also ensure that things don't break on existing HW.
I don't see our efforts being wasted in trying to make Linux RISC-V feature
complete and encouraging more feature rich RISC-V CPUs.
Delays in merging patches are fine as long as people have something to try
on their RISC-V CPU implementations.
>
> Seriously, they say "walk before you can run", but this is more "crawl before
> you can fly". What's the rush?
>
> Will
Regards,
Anup
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