On Mon, Sep 30, 2019 at 9:11 AM Robin Murphy <[email protected]> wrote: > > Whilst Midgard's MEMATTR follows a similar principle to the VMSA MAIR, > the actual attribute values differ, so although it currently appears to > work to some degree, we probably shouldn't be using our standard stage 1 > MAIR for that. Instead, generate a reasonable MEMATTR with attribute > values borrowed from the kbase driver; at this point we'll be overriding > or ignoring pretty much all of the LPAE config, so just implement these > Mali details in a dedicated allocator instead of pretending to subclass > the standard VMSA format. > > Fixes: d08d42de6432 ("iommu: io-pgtable: Add ARM Mali midgard MMU page table > format") > Tested-by: Neil Armstrong <[email protected]> > Reviewed-by: Steven Price <[email protected]> > Signed-off-by: Robin Murphy <[email protected]> > --- > drivers/iommu/io-pgtable-arm.c | 53 +++++++++++++++++++++++++--------- > 1 file changed, 40 insertions(+), 13 deletions(-)
Reviewed-by: Rob Herring <[email protected]> _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
