From: "Angelo G. Del Regno" <[email protected]>
Add a function to change the IOMMU pagetable addressing to
AArch32 LPAE or AArch64. If doing that, then this must be
done for each IOMMU context (not necessarily at the same time).
---
drivers/firmware/qcom_scm-32.c | 6 ++++++
drivers/firmware/qcom_scm-64.c | 15 +++++++++++++++
drivers/firmware/qcom_scm.c | 7 +++++++
drivers/firmware/qcom_scm.h | 4 ++++
drivers/firmware/qcom_scm.h.rej | 13 +++++++++++++
include/linux/qcom_scm.h | 2 ++
include/linux/qcom_scm.h.rej | 19 +++++++++++++++++++
7 files changed, 66 insertions(+)
create mode 100644 drivers/firmware/qcom_scm.h.rej
create mode 100644 include/linux/qcom_scm.h.rej
diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index 215061c581e1..f5437e5c8c4e 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -597,6 +597,12 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev,
u64 addr, u32 size,
return -ENODEV;
}
+int __qcom_scm_iommu_set_pt_format(struct device *dev, u32 sec_id, u32 ctx_num,
+ u32 pt_fmt)
+{
+ return -ENODEV;
+}
+
int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
unsigned int *val)
{
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index 91d5ad7cf58b..aab5446ea9f2 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -459,6 +459,21 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev,
u64 addr, u32 size,
return ret;
}
+int __qcom_scm_iommu_set_pt_format(struct device *dev, u32 sec_id, u32 ctx_num,
+ u32 pt_fmt)
+{
+ struct qcom_scm_desc desc = {0};
+ struct arm_smccc_res res;
+
+ desc.args[0] = sec_id;
+ desc.args[1] = ctx_num;
+ desc.args[2] = pt_fmt; /* 0: LPAE AArch32 - 1: AArch64 */
+ desc.arginfo = QCOM_SCM_ARGS(3);
+
+ return qcom_scm_call(dev, QCOM_SCM_SVC_SMMU_PROGRAM,
+ QCOM_SCM_IOMMU_PT_FORMAT, &desc, &res);
+}
+
int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
{
struct qcom_scm_desc desc = {0};
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 4802ab170fe5..41af7dc0b34d 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -345,6 +345,13 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size,
u32 spare)
}
EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
+int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt)
+{
+ return __qcom_scm_iommu_set_pt_format(__scm->dev, sec_id,
+ ctx_num, pt_fmt);
+}
+EXPORT_SYMBOL(qcom_scm_iommu_set_pt_format);
+
int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
{
return __qcom_scm_io_readl(__scm->dev, addr, val);
diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
index 99506bd873c0..f04a3903dc6c 100644
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -95,6 +95,10 @@ extern int __qcom_scm_iommu_secure_ptbl_size(struct device
*dev, u32 spare,
size_t *size);
extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
u32 size, u32 spare);
+#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
+#define QCOM_SCM_IOMMU_PT_FORMAT 1
+extern int __qcom_scm_iommu_set_pt_format(struct device *dev, u32 sec_id,
+ u32 ctx_num, u32 pt_fmt);
#define QCOM_MEM_PROT_ASSIGN_ID 0x16
extern int __qcom_scm_assign_mem(struct device *dev,
phys_addr_t mem_region, size_t mem_sz,
diff --git a/drivers/firmware/qcom_scm.h.rej b/drivers/firmware/qcom_scm.h.rej
new file mode 100644
index 000000000000..05bb1a91dca5
--- /dev/null
+++ b/drivers/firmware/qcom_scm.h.rej
@@ -0,0 +1,13 @@
+--- drivers/firmware/qcom_scm.h
++++ drivers/firmware/qcom_scm.h
+@@ -98,6 +98,10 @@ extern int __qcom_scm_iommu_secure_ptbl_init(struct device
*dev, u64 addr,
+ u32 size, u32 spare);
+ extern int __qcom_scm_iommu_set_cp_pool_size(struct device *dev, u32 spare,
+ u32 size);
++#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
++#define QCOM_SCM_IOMMU_PT_FORMAT 1
++extern int __qcom_scm_iommu_set_pt_format(struct device *dev, u32 sec_id,
++ u32 ctx_num, u32 pt_fmt);
+ #define QCOM_MEM_PROT_ASSIGN_ID 0x16
+ extern int __qcom_scm_assign_mem(struct device *dev,
+ phys_addr_t mem_region, size_t mem_sz,
diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
index 2d5eff506e13..49937d62e462 100644
--- a/include/linux/qcom_scm.h
+++ b/include/linux/qcom_scm.h
@@ -58,6 +58,7 @@ extern int qcom_scm_set_remote_state(u32 state, u32 id);
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
+extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
#else
@@ -97,6 +98,7 @@ qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV;
}
static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return
-ENODEV; }
static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) {
return -ENODEV; }
static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32
spare) { return -ENODEV; }
+static inline int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32
pt_fmt) { return -ENODEV; }
static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) {
return -ENODEV; }
static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) {
return -ENODEV; }
#endif
diff --git a/include/linux/qcom_scm.h.rej b/include/linux/qcom_scm.h.rej
new file mode 100644
index 000000000000..138b48e29999
--- /dev/null
+++ b/include/linux/qcom_scm.h.rej
@@ -0,0 +1,19 @@
+--- include/linux/qcom_scm.h
++++ include/linux/qcom_scm.h
+@@ -59,6 +59,7 @@ extern int qcom_scm_restore_sec_cfg(u32 device_id, u32
spare);
+ extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
+ extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
+ extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
++extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
+ extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
+ extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
+ #else
+@@ -99,6 +100,8 @@ static inline int qcom_scm_restore_sec_cfg(u32 device_id,
u32 spare) { return -E
+ static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) {
return -ENODEV; }
+ static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32
spare) { return -ENODEV; }
+ static inline int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size) {
return -ENODEV; }
++static inline int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num,
++ u32 pt_fmt) { return -ENODEV; }
+ static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) {
return -ENODEV; }
+ static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) {
return -ENODEV; }
+ #endif
--
2.21.0
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