On Mon, Nov 04, 2019 at 04:40:06PM -0700, Jordan Crouse wrote:
> On Fri, Oct 25, 2019 at 07:08:39PM +0100, Robin Murphy wrote:
> > Now that we can correctly extract top-level indices without relying on
> > the remaining upper bits being zero, the only remaining impediments to
> > using a given table for TTBR1 are the address validation on map/unmap
> > and the awkward TCR translation granule format. Add a quirk so that we
> > can do the right thing at those points.
>
> This looks great. I have one comment about the TCR.A1 bit below but otherwise
> this is sane. My immediate todo this week and next is to try to get something
> spun up and working on the db845 for verification.
How did that go?
> > @@ -800,15 +812,16 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg
> > *cfg, void *cookie)
> > tcr->orgn = ARM_LPAE_TCR_RGN_NC;
> > }
> >
> > + tg1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1;
> > switch (ARM_LPAE_GRANULE(data)) {
> > case SZ_4K:
> > - tcr->tg = ARM_LPAE_TCR_TG0_4K;
> > + tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_4K : ARM_LPAE_TCR_TG0_4K;
> > break;
> > case SZ_16K:
> > - tcr->tg = ARM_LPAE_TCR_TG0_16K;
> > + tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_16K : ARM_LPAE_TCR_TG0_16K;
> > break;
> > case SZ_64K:
> > - tcr->tg = ARM_LPAE_TCR_TG0_64K;
> > + tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_64K : ARM_LPAE_TCR_TG0_64K;
> > break;
> > }
>
> The comment in one of the previous patches about the ASID in TTBR1 triggered
> something in my brain. v2 TCR A1,bit[22] controls from which TTBR the ASID is
> used I'm not sure if that qualifies as a quirk here or if it should be
> entirely
> handled within arm_smmu_lpae_tcr() but I thought I should point it out.
That should be confined entirely to the driver code though, no? The
io-pgtable code doesn't go near ASIDs or the A1 bit.
Will
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