Merge pasid cache invalidation into iommu->flush.pc_inv. Signed-off-by: Lu Baolu <baolu...@linux.intel.com> --- drivers/iommu/intel-iommu.c | 13 +++++++++++++ drivers/iommu/intel-pasid.c | 18 ++---------------- include/linux/intel-iommu.h | 3 +++ 3 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index 59e4130161eb..283382584453 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -2994,6 +2994,18 @@ qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, qi_submit_sync(&desc, iommu); } +/* PASID cache invalidation */ +static void +qi_flush_pasid(struct intel_iommu *iommu, u16 did, u32 pasid, u64 granu) +{ + struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0}; + + desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) | + QI_PC_GRAN(granu) | QI_PC_TYPE; + + qi_submit_sync(&desc, iommu); +} + static void intel_iommu_init_qi(struct intel_iommu *iommu) { /* @@ -3025,6 +3037,7 @@ static void intel_iommu_init_qi(struct intel_iommu *iommu) } else { iommu->flush.cc_inv = qi_flush_context; iommu->flush.iotlb_inv = qi_flush_iotlb; + iommu->flush.pc_inv = qi_flush_pasid; pr_info("%s: Using Queued invalidation\n", iommu->name); } } diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c index 3cb569e76642..dd736f673603 100644 --- a/drivers/iommu/intel-pasid.c +++ b/drivers/iommu/intel-pasid.c @@ -359,20 +359,6 @@ pasid_set_flpm(struct pasid_entry *pe, u64 value) pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2); } -static void -pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, - u16 did, int pasid) -{ - struct qi_desc desc; - - desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid); - desc.qw1 = 0; - desc.qw2 = 0; - desc.qw3 = 0; - - qi_submit_sync(&desc, iommu); -} - static void iotlb_invalidation_with_pasid(struct intel_iommu *iommu, u16 did, u32 pasid) { @@ -421,7 +407,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, if (!ecap_coherent(iommu->ecap)) clflush_cache_range(pte, sizeof(*pte)); - pasid_cache_invalidation_with_pasid(iommu, did, pasid); + iommu->flush.pc_inv(iommu, did, pasid, QI_PC_GRAN_PSWD); iotlb_invalidation_with_pasid(iommu, did, pasid); /* Device IOTLB doesn't need to be flushed in caching mode. */ @@ -437,7 +423,7 @@ static void pasid_flush_caches(struct intel_iommu *iommu, clflush_cache_range(pte, sizeof(*pte)); if (cap_caching_mode(iommu->cap)) { - pasid_cache_invalidation_with_pasid(iommu, did, pasid); + iommu->flush.pc_inv(iommu, did, pasid, QI_PC_GRAN_PSWD); iotlb_invalidation_with_pasid(iommu, did, pasid); } else { iommu_flush_write_buffer(iommu); diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index ac725a4ce1c1..c32ff2a7d958 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -344,6 +344,9 @@ enum { #define QI_PC_PASID(pasid) (((u64)pasid) << 32) #define QI_PC_DID(did) (((u64)did) << 16) #define QI_PC_GRAN(gran) (((u64)gran) << 4) +#define QI_PC_GRAN_DS 0 +#define QI_PC_GRAN_PSWD 1 +#define QI_PC_GRAN_GLOBAL 3 #define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0)) #define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1)) -- 2.17.1 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu