Hi,
On 1/10/20 5:50 AM, Jacob Pan wrote:
On Thu, 19 Dec 2019 10:46:51 +0800
Lu Baolu<[email protected]> wrote:
Hi,
On 12/17/19 3:24 AM, Jacob Pan wrote:
When Shared Virtual Memory is exposed to a guest via vIOMMU,
scalable IOTLB invalidation may be passed down from outside IOMMU
subsystems. This patch adds invalidation functions that can be used
for additional translation cache types.
Signed-off-by: Jacob Pan<[email protected]>
---
drivers/iommu/dmar.c | 46
+++++++++++++++++++++++++++++++++++++++++++++
drivers/iommu/intel-pasid.c | 3 ++- include/linux/intel-iommu.h |
21 +++++++++++++++++---- 3 files changed, 65 insertions(+), 5
deletions(-)
diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
index 3acfa6a25fa2..f2f5d75da94a 100644
--- a/drivers/iommu/dmar.c
+++ b/drivers/iommu/dmar.c
@@ -1348,6 +1348,20 @@ void qi_flush_iotlb(struct intel_iommu
*iommu, u16 did, u64 addr, qi_submit_sync(&desc, iommu);
}
+/* PASID-based IOTLB Invalidate */
+void qi_flush_iotlb_pasid(struct intel_iommu *iommu, u16 did, u64
addr, u32 pasid,
+ unsigned int size_order, u64 granu, int ih)
+{
+ struct qi_desc desc = {.qw2 = 0, .qw3 = 0};
+
+ desc.qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
+ QI_EIOTLB_GRAN(granu) | QI_EIOTLB_TYPE;
+ desc.qw1 = QI_EIOTLB_ADDR(addr) | QI_EIOTLB_IH(ih) |
+ QI_EIOTLB_AM(size_order);
+
+ qi_submit_sync(&desc, iommu);
+}
There's another version of pasid-based iotlb invalidation.
https://lkml.org/lkml/2019/12/10/2128
Let's consider merging them.
Absolutely, the difference i see is that the granularity is explicit
here. Here we do invalidation request from the guest. Perhaps, we can
look at consolidation once this use case is supported?
Looks good to me. :-)
Best regards,
baolu
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