On Fri, Feb 14, 2020 at 06:44:51PM +0800, Adrian Huang wrote: > From: Adrian Huang <[email protected]> > > The SPA of the GCR3 table root pointer[51:31] masks 20 bits. However, > this requires 21 bits (Please see the AMD IOMMU specification). > This leads to the potential failure when the bit 51 of SPA of > the GCR3 table root pointer is 1'. > > Signed-off-by: Adrian Huang <[email protected]>
Applied, thanks. _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
