On some SoCs like MSM8939 with A405 adreno, there is a gfx_tbu clock needs to be on while doing TLB invalidate. Otherwise, TLBSYNC status will not be correctly reflected, causing the system to go into a bad state. Add it as an optional clock, so that platforms that have this clock can pass it over DT.
Signed-off-by: Shawn Guo <[email protected]> --- drivers/iommu/qcom_iommu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c index 0e2a96467767..2f6c6da7d540 100644 --- a/drivers/iommu/qcom_iommu.c +++ b/drivers/iommu/qcom_iommu.c @@ -45,6 +45,7 @@ struct qcom_iommu_dev { struct device *dev; struct clk *iface_clk; struct clk *bus_clk; + struct clk *tlb_clk; void __iomem *local_base; u32 sec_id; u8 num_ctxs; @@ -643,11 +644,20 @@ static int qcom_iommu_enable_clocks(struct qcom_iommu_dev *qcom_iommu) return ret; } + ret = clk_prepare_enable(qcom_iommu->tlb_clk); + if (ret) { + dev_err(qcom_iommu->dev, "Couldn't enable tlb_clk\n"); + clk_disable_unprepare(qcom_iommu->bus_clk); + clk_disable_unprepare(qcom_iommu->iface_clk); + return ret; + } + return 0; } static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu) { + clk_disable_unprepare(qcom_iommu->tlb_clk); clk_disable_unprepare(qcom_iommu->bus_clk); clk_disable_unprepare(qcom_iommu->iface_clk); } @@ -839,6 +849,12 @@ static int qcom_iommu_device_probe(struct platform_device *pdev) return PTR_ERR(qcom_iommu->bus_clk); } + qcom_iommu->tlb_clk = devm_clk_get(dev, "tlb"); + if (IS_ERR(qcom_iommu->tlb_clk)) { + dev_dbg(dev, "failed to get tlb clock\n"); + qcom_iommu->tlb_clk = NULL; + } + if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id", &qcom_iommu->sec_id)) { dev_err(dev, "missing qcom,iommu-secure-id property\n"); -- 2.17.1 _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
