On 7/1/20 11:33 PM, Jacob Pan wrote:
DevTLB flush can be used for both DMA request with and without PASIDs.
The former uses PASID#0 (RID2PASID), latter uses non-zero PASID for SVA

This patch adds a check for PASID value such that devTLB flush with
PASID is used for SVA case. This is more efficient in that multiple
PASIDs can be used by a single device, when tearing down a PASID entry
we shall flush only the devTLB specific to a PASID.

Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table")
Signed-off-by: Jacob Pan <jacob.jun....@linux.intel.com>

Acked-by: Lu Baolu <baolu...@linux.intel.com>

Best regards,

  drivers/iommu/intel/pasid.c | 11 ++++++++++-
  1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index c81f0f17c6ba..fa0154cce537 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -486,7 +486,16 @@ devtlb_invalidation_with_pasid(struct intel_iommu *iommu,
        qdep = info->ats_qdep;
        pfsid = info->pfsid;
- qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT);
+       /*
+        * When PASID 0 is used, it indicates RID2PASID(DMA request w/o PASID),
+        * devTLB flush w/o PASID should be used. For non-zero PASID under
+        * SVA usage, device could do DMA with multiple PASIDs. It is more
+        * efficient to flush devTLB specific to the PASID.
+        */
+       if (pasid == PASID_RID2PASID)
+               qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - 
+       else
+               qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid, qdep, 0, 64 
void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev,

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