On Tue, Sep 15, 2020 at 09:30:07AM -0700, Fenghua Yu wrote: > +Background > +========== > + > +Shared Virtual Addressing (SVA) allows the processor and device to use the > +same virtual addresses avoiding the need for software to translate virtual > +addresses to physical addresses. SVA is what PCIe calls Shared Virtual > +Memory (SVM). > + > +In addition to the convenience of using application virtual addresses > +by the device, it also doesn't require pinning pages for DMA. > +PCIe Address Translation Services (ATS) along with Page Request Interface > +(PRI) allow devices to function much the same way as the CPU handling > +application page-faults. For more information please refer to the PCIe > +specification Chapter 10: ATS Specification. > + > +Use of SVA requires IOMMU support in the platform. IOMMU also is required > +to support PCIe features ATS and PRI. ATS allows devices to cache > +translations for virtual addresses. The IOMMU driver uses the mmu_notifier() > +support to keep the device TLB cache and the CPU cache in sync. PRI allows > +the device to request paging the virtual address by using the CPU page tables > +before accessing the address.
That still reads funny, the "the device to request paging the virtual address" part. Do you mean that per chance here: "Before the device can access that address, the device uses the PRI in order to request the virtual address to be paged in into the CPU page tables." ? -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette _______________________________________________ iommu mailing list email@example.com https://lists.linuxfoundation.org/mailman/listinfo/iommu