> On Sep 25, 2020, at 03:44, Raj, Ashok <ashok....@intel.com> wrote:
> Hi Alex
>>> Apparently it also requires to disable RR, and I'm not able to confirm if
>>> CML requires that as well. 
>>> pci_quirk_disable_intel_spt_pch_acs_redir() also seems to consult the same
>>> table, so i'm not sure why we need the other patch in bugzilla is required.
>> If we're talking about the Intel bug where PCH root ports implement
>> the ACS capability and control registers as dword rather than word
>> registers, then how is ACS getting enabled in order to generate an ACS
>> violation?  The standard ACS code would write to the control register
>> word at offset 6, which is still the read-only capability register on
>> those devices.  Thanks,
> Right... Maybe we need header log to figure out what exatly is happening. 

Please let me know what logs you need.

As Bjorn mentioned earlier, there's currently no way to dump TLP header log?

iommu mailing list

Reply via email to