On Mon, Oct 05 2020 at 16:28, David Woodhouse wrote:
> From: David Woodhouse <[email protected]>
>
> This is the mask of CPUs to which IRQs can be delivered without interrupt
> remapping.
>
> +/* Mask of CPUs which can be targeted by non-remapped interrupts. */
> +cpumask_t x86_non_ir_cpumask = { CPU_BITS_ALL };
What?
> #ifdef CONFIG_X86_32
>
> /*
> @@ -1838,6 +1841,7 @@ static __init void x2apic_enable(void)
> static __init void try_to_enable_x2apic(int remap_mode)
> {
> u32 apic_limit = 0;
> + int i;
>
> if (x2apic_state == X2APIC_DISABLED)
> return;
> @@ -1880,6 +1884,14 @@ static __init void try_to_enable_x2apic(int remap_mode)
> if (apic_limit)
> x2apic_set_max_apicid(apic_limit);
>
> + /* Build the affinity mask for interrupts that can't be remapped. */
> + cpumask_clear(&x86_non_ir_cpumask);
> + i = min_t(unsigned int, num_possible_cpus() - 1, apic_limit);
> + for ( ; i >= 0; i--) {
> + if (cpu_physical_id(i) <= apic_limit)
> + cpumask_set_cpu(i, &x86_non_ir_cpumask);
> + }
Blink. If the APIC id is not linear with the cpu numbers then this
results in a reduced addressable set of CPUs. WHY?
> diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
> index aa9a3b54a96c..4d0ef46fedb9 100644
> --- a/arch/x86/kernel/apic/io_apic.c
> +++ b/arch/x86/kernel/apic/io_apic.c
> @@ -2098,6 +2098,8 @@ static int mp_alloc_timer_irq(int ioapic, int pin)
> struct irq_alloc_info info;
>
> ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
> + if (domain->parent == x86_vector_domain)
> + info.mask = &x86_non_ir_cpumask;
We are not going to sprinkle such domain checks all over the
place. Again, the mask is a property of the interrupt domain.
Thanks,
tglx
_______________________________________________
iommu mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/iommu
