If the iova is 34bit, the iova[32][33] is the bit0/1 in the tlb flush
register. Add a new macro for this.

there is a minor change unrelated with this patch. it also use the new
macro.

Signed-off-by: Yong Wu <yong...@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 46c9143703a9..11af0780e4dd 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -128,6 +128,9 @@ static const struct iommu_ops mtk_iommu_ops;
 
 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data);
 
+#define MTK_IOMMU_ADDR(addr) ({unsigned long _addr = addr; \
+                             (lower_32_bits(_addr) | upper_32_bits(_addr)); })
+
 /*
  * In M4U 4GB mode, the physical address is remapped as below:
  *
@@ -218,8 +221,9 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long 
iova, size_t size,
                writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
                               data->base + data->plat_data->inv_sel_reg);
 
-               writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
-               writel_relaxed(iova + size - 1,
+               writel_relaxed(MTK_IOMMU_ADDR(iova),
+                              data->base + REG_MMU_INVLD_START_A);
+               writel_relaxed(MTK_IOMMU_ADDR(iova + size - 1),
                               data->base + REG_MMU_INVLD_END_A);
                writel_relaxed(F_MMU_INV_RANGE,
                               data->base + REG_MMU_INVALIDATE);
@@ -639,8 +643,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data 
*data)
        if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
                regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
        else
-               regval = lower_32_bits(data->protect_base) |
-                        upper_32_bits(data->protect_base);
+               regval = MTK_IOMMU_ADDR(data->protect_base);
        writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
 
        if (data->enable_4GB &&
-- 
2.18.0

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