This patch adds two variables in the plat_data:
bank_nr: the bank number that this SoC support;
bank_enable: list if the banks is enabled.

This patch add them for all the current SoC, bank_nr always is 1 and
only bank_enable[0] is enabled. it is preparing for supporting
multi banks.

Signed-off-by: Yong Wu <[email protected]>
---
 drivers/iommu/mtk_iommu.c | 18 ++++++++++++++++++
 drivers/iommu/mtk_iommu.h |  3 +++
 2 files changed, 21 insertions(+)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index ed3cf75850ce..042489b8e402 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1116,6 +1116,8 @@ static const struct mtk_iommu_plat_data mt2712_data = {
                        NOT_STD_AXI_MODE | MTK_IOMMU_TYPE_MM,
        .hw_list      = &m4ulist,
        .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
+       .bank_nr      = 1,
+       .bank_enable  = {true},
        .iova_region  = single_domain,
        .iova_region_nr = ARRAY_SIZE(single_domain),
        .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
@@ -1126,6 +1128,8 @@ static const struct mtk_iommu_plat_data mt6779_data = {
        .flags         = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
                         NOT_STD_AXI_MODE | MTK_IOMMU_TYPE_MM,
        .inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
+       .bank_nr       = 1,
+       .bank_enable   = {true},
        .iova_region   = single_domain,
        .iova_region_nr = ARRAY_SIZE(single_domain),
        .larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
@@ -1136,6 +1140,8 @@ static const struct mtk_iommu_plat_data mt8167_data = {
        .flags        = RESET_AXI | HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE |
                        MTK_IOMMU_TYPE_MM,
        .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
+       .bank_nr      = 1,
+       .bank_enable  = {true},
        .iova_region  = single_domain,
        .iova_region_nr = ARRAY_SIZE(single_domain),
        .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
@@ -1147,6 +1153,8 @@ static const struct mtk_iommu_plat_data mt8173_data = {
                        HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE |
                        MTK_IOMMU_TYPE_MM,
        .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
+       .bank_nr      = 1,
+       .bank_enable  = {true},
        .iova_region  = single_domain,
        .iova_region_nr = ARRAY_SIZE(single_domain),
        .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
@@ -1156,6 +1164,8 @@ static const struct mtk_iommu_plat_data mt8183_data = {
        .m4u_plat     = M4U_MT8183,
        .flags        = RESET_AXI | MTK_IOMMU_TYPE_MM,
        .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
+       .bank_nr      = 1,
+       .bank_enable  = {true},
        .iova_region  = single_domain,
        .iova_region_nr = ARRAY_SIZE(single_domain),
        .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
@@ -1167,6 +1177,8 @@ static const struct mtk_iommu_plat_data mt8192_data = {
                          WR_THROT_EN | IOVA_34_EN | NOT_STD_AXI_MODE |
                          MTK_IOMMU_TYPE_MM,
        .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
+       .bank_nr        = 1,
+       .bank_enable    = {true},
        .iova_region    = mt8192_multi_dom,
        .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
        .larbid_remap   = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
@@ -1178,6 +1190,8 @@ static const struct mtk_iommu_plat_data mt8195_data_infra 
= {
        .flags            = WR_THROT_EN | DCM_DISABLE |
                            MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIe_SUPPORT,
        .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
+       .bank_nr          = 1,
+       .bank_enable      = {true},
        .inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
        .iova_region      = single_domain,
        .iova_region_nr   = ARRAY_SIZE(single_domain),
@@ -1190,6 +1204,8 @@ static const struct mtk_iommu_plat_data mt8195_data_vdo = 
{
                          MTK_IOMMU_TYPE_MM,
        .hw_list        = &m4ulist,
        .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
+       .bank_nr        = 1,
+       .bank_enable    = {true},
        .iova_region    = mt8192_multi_dom,
        .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
        .larbid_remap   = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
@@ -1203,6 +1219,8 @@ static const struct mtk_iommu_plat_data mt8195_data_vdp = 
{
                          MTK_IOMMU_TYPE_MM,
        .hw_list        = &m4ulist,
        .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
+       .bank_nr        = 1,
+       .bank_enable    = {true},
        .iova_region    = mt8192_multi_dom,
        .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
        .larbid_remap   = {{1}, {3}, {22, 0, 0, 0, 23}, {8},
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 7193278501dd..78d9481d67b5 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -62,6 +62,9 @@ struct mtk_iommu_plat_data {
        struct list_head                        *hw_list;
        unsigned int                            iova_region_nr;
        const struct mtk_iommu_iova_region      *iova_region;
+
+       u32                 bank_nr;
+       bool                bank_enable[MTK_IOMMU_BANK_MAX];
        unsigned char       larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
 };
 
-- 
2.18.0

_______________________________________________
iommu mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/iommu

Reply via email to