On Fri, Oct 08, 2021 at 12:54:52AM +1300, Barry Song wrote: > On Fri, Oct 8, 2021 at 12:32 AM Jason Gunthorpe <j...@nvidia.com> wrote: > > > > On Thu, Oct 07, 2021 at 06:43:33PM +1300, Barry Song wrote: > > > > > So do we have a case where devices can directly access the kernel's data > > > structure such as a list/graph/tree with pointers to a kernel virtual > > > address? > > > then devices don't need to translate the address of pointers in a > > > structure. > > > I assume this is one of the most useful features userspace SVA can > > > provide. > > > > AFIACT that is the only good case for KVA, but it is also completely > > against the endianess, word size and DMA portability design of the > > kernel. > > > > Going there requires some new set of portable APIs for gobally > > coherent KVA dma. > > yep. I agree. it would be very weird if accelerators/gpu are sharing > kernel' data struct, but for each "DMA" operation - reading or writing > the data struct, we have to call dma_map_single/sg or > dma_sync_single_for_cpu/device etc. It seems once devices and cpus > are sharing virtual address(SVA), code doesn't need to do explicit > map/sync each time.
No, it still need to do something to manage visibility from the current CPU to the DMA - it might not be flushing a cache, but it is probably a arch specific CPU barrier instruction. Jason _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu