On Mon, Feb 14, 2022 at 08:55:20PM +0800, Yicong Yang wrote: > On 2022/1/24 21:11, Yicong Yang wrote: > > The DMA of HiSilicon PTT device can only work with identical > > mapping. So add a quirk for the device to force the domain > > passthrough. > > > > Signed-off-by: Yicong Yang <[email protected]> > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index 6dc6d8b6b368..6f67a2b1dd27 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -2838,6 +2838,21 @@ static int arm_smmu_dev_disable_feature(struct > > device *dev, > > } > > } > > > > +#define IS_HISI_PTT_DEVICE(pdev) ((pdev)->vendor == PCI_VENDOR_ID_HUAWEI > > && \ > > + (pdev)->device == 0xa12e) > > + > > +static int arm_smmu_def_domain_type(struct device *dev) > > +{ > > + if (dev_is_pci(dev)) { > > + struct pci_dev *pdev = to_pci_dev(dev); > > + > > + if (IS_HISI_PTT_DEVICE(pdev)) > > + return IOMMU_DOMAIN_IDENTITY; > > + } > > + > > + return 0; > > +} > > + > > static struct iommu_ops arm_smmu_ops = { > > .capable = arm_smmu_capable, > > .domain_alloc = arm_smmu_domain_alloc, > > @@ -2863,6 +2878,7 @@ static struct iommu_ops arm_smmu_ops = { > > .sva_unbind = arm_smmu_sva_unbind, > > .sva_get_pasid = arm_smmu_sva_get_pasid, > > .page_response = arm_smmu_page_response, > > + .def_domain_type = arm_smmu_def_domain_type, > > .pgsize_bitmap = -1UL, /* Restricted during device attach */ > > .owner = THIS_MODULE, > > }; > > > > Is this quirk ok with the SMMU v3 driver? Just want to confirm that I'm on the > right way to dealing with the issue of our device.
I don't think the quirk should be in the SMMUv3 driver. Assumedly, you would have the exact same problem if you stuck the PTT device behind a different type of IOMMU, and so the quirk should be handled by a higher level of the stack. Will _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
