Hi Jason, On Tue, 15 Mar 2022 11:22:16 -0300, Jason Gunthorpe <j...@nvidia.com> wrote:
> On Tue, Mar 15, 2022 at 11:16:41AM +0000, Robin Murphy wrote: > > On 2022-03-15 05:07, Jacob Pan wrote: > > > DMA mapping API is the de facto standard for in-kernel DMA. It > > > operates on a per device/RID basis which is not PASID-aware. > > > > > > Some modern devices such as Intel Data Streaming Accelerator, PASID is > > > required for certain work submissions. To allow such devices use DMA > > > mapping API, we need the following functionalities: > > > 1. Provide device a way to retrieve a PASID for work submission within > > > the kernel > > > 2. Enable the kernel PASID on the IOMMU for the device > > > 3. Attach the kernel PASID to the device's default DMA domain, let it > > > be IOVA or physical address in case of pass-through. > > > > > > This patch introduces a driver facing API that enables DMA API > > > PASID usage. Once enabled, device drivers can continue to use DMA > > > APIs as is. There is no difference in dma_handle between without > > > PASID and with PASID. > > > > Surely the main point of PASIDs is to be able to use more than one > > of them? > > IMHO, not for the DMA API. > Right, but we really need two here. One for DMA request w/o PASID (PASID 0) and a kernel PASID for DMA request tagged w/ PASID. Since DMA API is not per process, there is no need for more right now. > I can't think of good reasons why a single in-kernel device should > require more than one iommu_domain for use by the DMA API. Even with > the SIOV cases we have been looking at we don't really see a use case > for more than one DMA API iommu_domain on a single physical device. > Do you know of something on the horizon? > Not that I know. > From my view the main point of PASIDs is to assign iommu_domains that > are not used by the DMA API. > Right, DMA API default to PASID 0. But IDXD device cannot use PASID 0 for enqcmds. > IMHO it is a device mis-design of IDXD to require all DMA be PASID > tagged. Devices should be able to do DMA on their RID when the PCI IDXD can do DMA w/ RID, the PASID requirement is only for shared WQ where ENQCMDS is used. ENQCMDS has the benefit of avoiding locking where work submission is done from multiple CPUs. Tony, Dave? > function is controlled by a kernel driver. I see this driver facing > API as addressing a device quirk by aliasing the DMA API of the RID > into a PASID and that is really all it is good for. > > In any case I think we are better to wait for an actual user for multi > DMA API iommu_domains to come forward before we try to build an API > for it. > What would you recommend in the interim? Shall we let VT-d driver set up a special global PASID for DMA API? Then IDXD driver can retrieve it somehow? But that still needs an API similar to what I did in the previous version where PASID #1 was used. Thanks, Jacob _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu