On Mon, Apr 11, 2022 at 12:25:41PM +0530, Rohit Agarwal wrote:
> Add a node for the ARM SMMU found in the SDX65.
> 
> Signed-off-by: Rohit Agarwal <[email protected]>
> ---
>  arch/arm/boot/dts/qcom-sdx65.dtsi | 40 
> +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi 
> b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 632ac78..2481769 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -181,6 +181,46 @@
>                       status = "disabled";
>               };
>  
> +             apps_smmu: iommu@15000000 {

Please sort the nodes in ascending order.

Thanks,
Mani

> +                     compatible = "qcom,sdx65-smmu-500", "arm,mmu-500";
> +                     reg = <0x15000000 0x40000>;
> +                     #iommu-cells = <2>;
> +                     #global-interrupts = <1>;
> +                     interrupts =    <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> +                                     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> +             };
> +
>               pdc: interrupt-controller@b210000 {
>                       compatible = "qcom,sdx65-pdc", "qcom,pdc";
>                       reg = <0xb210000 0x10000>;
> -- 
> 2.7.4
> 
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