> From: Lu Baolu > Sent: Thursday, April 21, 2022 7:36 PM > > PRQ overflow may cause I/O throughput congestion, resulting in unnecessary > degradation of I/O performance. Appropriately increasing the length of PRQ > can greatly reduce the occurrence of PRQ overflow. The count of maximum > page requests that can be generated in parallel by a PCIe device is > statically defined in the Outstanding Page Request Capacity field of the > PCIe ATS configure space. > > The new length of PRQ is calculated by summing up the value of Outstanding > Page Request Capacity register across all devices where Page Requests are > supported on the real PR-capable platform (Intel Sapphire Rapids). The > result is round to the nearest higher power of 2. > > The PRQ length is also double sized as the VT-d IOMMU driver only updates > the Page Request Queue Head Register (PQH_REG) after processing the > entire > queue. > > Signed-off-by: Lu Baolu <baolu...@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.t...@intel.com> > --- > include/linux/intel-svm.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/linux/intel-svm.h b/include/linux/intel-svm.h > index b3b125b332aa..207ef06ba3e1 100644 > --- a/include/linux/intel-svm.h > +++ b/include/linux/intel-svm.h > @@ -9,7 +9,7 @@ > #define __INTEL_SVM_H__ > > /* Page Request Queue depth */ > -#define PRQ_ORDER 2 > +#define PRQ_ORDER 4 > #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20) > #define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5) > > -- > 2.25.1 > > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
