On Mon, 2022-05-16 at 22:16 +0800, yf.w...@mediatek.com wrote:
> From: Yunfei Wang <yf.w...@mediatek.com>
> 
> Add the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT support, so that
> allows
> page table PA up to 35bit, not only in ZONE_DMA32.

Comment why this is needed.

e.g. For single normal zone.

> 
> Signed-off-by: Ning Li <ning...@mediatek.com>
> Signed-off-by: Yunfei Wang <yf.w...@mediatek.com>
> ---
>  drivers/iommu/mtk_iommu.c | 29 +++++++++++++++++++++++++----
>  1 file changed, 25 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 6fd75a60abd6..1b9a876ef271 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -33,6 +33,7 @@
>  
>  #define REG_MMU_PT_BASE_ADDR                 0x000
>  #define MMU_PT_ADDR_MASK                     GENMASK(31, 7)
> +#define MMU_PT_ADDR_2_0_MASK                 GENMASK(2, 0)
>  
>  #define REG_MMU_INVALIDATE                   0x020
>  #define F_ALL_INVLD                          0x2
> @@ -118,6 +119,7 @@
>  #define WR_THROT_EN                  BIT(6)
>  #define HAS_LEGACY_IVRP_PADDR                BIT(7)
>  #define IOVA_34_EN                   BIT(8)
> +#define PGTABLE_PA_35_EN             BIT(9)
>  
>  #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
>               ((((pdata)->flags) & (_x)) == (_x))
> @@ -401,6 +403,9 @@ static int mtk_iommu_domain_finalise(struct
> mtk_iommu_domain *dom,
>               .iommu_dev = data->dev,
>       };
>  
> +     if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
> +             dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
> +
>       if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
>               dom->cfg.oas = data->enable_4GB ? 33 : 32;
>       else
> @@ -450,6 +455,7 @@ static int mtk_iommu_attach_device(struct
> iommu_domain *domain,
>       struct mtk_iommu_domain *dom = to_mtk_domain(domain);
>       struct device *m4udev = data->dev;
>       int ret, domid;
> +     u32 regval;
>  
>       domid = mtk_iommu_get_domain_id(dev, data->plat_data);
>       if (domid < 0)
> @@ -472,8 +478,14 @@ static int mtk_iommu_attach_device(struct
> iommu_domain *domain,
>                       return ret;
>               }
>               data->m4u_dom = dom;
> -             writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
> -                    data->base + REG_MMU_PT_BASE_ADDR);
> +
> +             /* Bits[6:3] are invalid for mediatek platform */
> +             if (MTK_IOMMU_HAS_FLAG(data->plat_data,
> PGTABLE_PA_35_EN))
> +                     regval = (dom->cfg.arm_v7s_cfg.ttbr &
> MMU_PT_ADDR_MASK) |
> +                              (dom->cfg.arm_v7s_cfg.ttbr &
> MMU_PT_ADDR_2_0_MASK);

The bits[2:0] has already handled in ARM_V7S_TTBR_35BIT_PA of
patch[1/2], we need calculate it again here?

1) Extend arm_v7s_cfg.ttbr to u64, then we could put the special ttbr
logical into our file.

2) if 1) is not allowed, We have to put this in v7s.
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) {
       cfg->arm_v7s_cfg.ttbr = (paddr & GENMASK(31, 7)) |
upper_32_bits(paddr);
       return &data->iop;
}

This need Robin/Will confirm.

> +             else
> +                     regval = dom->cfg.arm_v7s_cfg.ttbr &
> MMU_PT_ADDR_MASK;

Save this value to our data. then we don't need calculate it again in
the resume cb.   

> +             writel(regval, data->base + REG_MMU_PT_BASE_ADDR);
>  
>               pm_runtime_put(m4udev);
>       }
> @@ -987,6 +999,7 @@ static int __maybe_unused
> mtk_iommu_runtime_resume(struct device *dev)
>       struct mtk_iommu_suspend_reg *reg = &data->reg;
>       struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
>       void __iomem *base = data->base;
> +     u32 regval;
>       int ret;
>  
>       ret = clk_prepare_enable(data->bclk);
> @@ -1010,7 +1023,14 @@ static int __maybe_unused
> mtk_iommu_runtime_resume(struct device *dev)
>       writel_relaxed(reg->int_main_control, base +
> REG_MMU_INT_MAIN_CONTROL);
>       writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
>       writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
> -     writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base +
> REG_MMU_PT_BASE_ADDR);
> +
> +     /* Bits[6:3] are invalid for mediatek platform */
> +     if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
> +             regval = (m4u_dom->cfg.arm_v7s_cfg.ttbr &
> MMU_PT_ADDR_MASK) |
> +                      (m4u_dom->cfg.arm_v7s_cfg.ttbr &
> MMU_PT_ADDR_2_0_MASK);
> +     else
> +             regval = m4u_dom->cfg.arm_v7s_cfg.ttbr &
> MMU_PT_ADDR_MASK;
> +     writel(regval, base + REG_MMU_PT_BASE_ADDR);
>  
>       /*
>        * Users may allocate dma buffer before they call
> pm_runtime_get,
> @@ -1038,7 +1058,8 @@ static const struct mtk_iommu_plat_data
> mt2712_data = {
>  
>  static const struct mtk_iommu_plat_data mt6779_data = {
>       .m4u_plat      = M4U_MT6779,
> -     .flags         = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,
> +     .flags         = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN |
> +                      PGTABLE_PA_35_EN,
>       .inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
>       .iova_region   = single_domain,
>       .iova_region_nr = ARRAY_SIZE(single_domain),

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